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    SEMICONDUCTOR DEVICES
    1.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240306374A1

    公开(公告)日：2024-09-12

    申请号：US18414655

    申请日：2024-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KEUNNAM KIM ,  Seungbo Ko ,  Jongmin Kim ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Myeongdong Lee

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

    Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.

    INTEGRATED CIRCUIT DEVICE
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20220336465A1

    公开(公告)日：2022-10-20

    申请号：US17667195

    申请日：2022-02-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

    IPC: H01L27/108 ,  H01L23/528

    Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

    SEMICONDUCTOR DEVICES
    4.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240315006A1

    公开(公告)日：2024-09-19

    申请号：US18424447

    申请日：2024-01-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Junhyeok Ahn ,  Chansic Yoon ,  Myeongdong Lee

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

    Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate, a first contact structure on a central portion of each active pattern, a bit line structure on the first contact structure, a second contact structure on an end portion of each active pattern, a third contact structure on the second contact structure, a filling pattern between the bit line structure and the third contact structure and including a void, and a capacitor electrically connected to the third contact structure. The active pattern array includes active pattern rows spaced apart from each other in a first direction, and each active pattern row includes the active patterns spaced apart from each other in a second direction. Each active pattern extends in a third direction, and the active patterns in each active pattern row are aligned in the second direction.

    Semiconductor devices including an edge insulating layer
    5.
    发明授权
    Semiconductor devices including an edge insulating layer 有权

    公开(公告)号：US11770926B2

    公开(公告)日：2023-09-26

    申请号：US17530818

    申请日：2021-11-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyeok Ahn ,  Kiseok Lee ,  Huijung Kim

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

    Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

    Semiconductor devices having buried gates
    6.
    发明授权
    Semiconductor devices having buried gates 有权

    公开(公告)号：US11626409B2

    公开(公告)日：2023-04-11

    申请号：US17318563

    申请日：2021-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

    IPC: H01L27/108 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

    Semiconductor devices
    7.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11037930B2

    公开(公告)日：2021-06-15

    申请号：US16670232

    申请日：2019-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Keunnam Kim ,  Huijung Kim ,  Sohyun Park ,  Jaehwan Cho ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a contact plug structure being adjacent to the bit line structure and extending in a vertical direction perpendicular to an upper surface of the substrate, and a capacitor electrically connected to the contact plug structure. The contact plug structure includes a lower contact plug, a metal silicide pattern, and an upper contact plug that are sequentially stacked on the substrate. The metal silicide pattern has an L-shaped cross section.

    SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250098146A1

    公开(公告)日：2025-03-20

    申请号：US18815974

    申请日：2024-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun Lee ,  Kiseok Lee ,  Huijung Kim ,  Younggeun Song ,  Yongjin Lee

    IPC: H10B12/00

    Abstract: A semiconductor device includes bit lines, channels, a first capping pattern, a gate insulation pattern, a gate electrode and capacitors. The bit lines are on a substrate, and each of the bit lines extends in a first direction. The bit lines are spaced apart from each other in a second direction. The channels are spaced apart from each other in the first direction. The first capping pattern is on a sidewall of each of the channels. The gate insulation pattern is on a sidewall of the first capping pattern. The gate electrode is on a sidewall of the gate insulation pattern. The capacitors are electrically connected to respective ones of the channels.

    Integrated circuit device
    9.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12114475B2

    公开(公告)日：2024-10-08

    申请号：US17667195

    申请日：2022-02-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

    IPC: H01L23/528 ,  H10B12/00 ,  H01L23/522

    CPC classification number: H10B12/0335 ,  H01L23/528 ,  H10B12/315 ,  H10B12/482 ,  H01L23/5226

    Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

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