公开(公告)号：US12114475B2

公开(公告)日：2024-10-08

申请号：US17667195

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

IPC: H01L23/528 ,  H10B12/00 ,  H01L23/522

CPC classification number: H10B12/0335 ,  H01L23/528 ,  H10B12/315 ,  H10B12/482 ,  H01L23/5226

Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

公开(公告)号：US20240315006A1

公开(公告)日：2024-09-19

申请号：US18424447

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Junhyeok Ahn ,  Chansic Yoon ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate, a first contact structure on a central portion of each active pattern, a bit line structure on the first contact structure, a second contact structure on an end portion of each active pattern, a third contact structure on the second contact structure, a filling pattern between the bit line structure and the third contact structure and including a void, and a capacitor electrically connected to the third contact structure. The active pattern array includes active pattern rows spaced apart from each other in a first direction, and each active pattern row includes the active patterns spaced apart from each other in a second direction. Each active pattern extends in a third direction, and the active patterns in each active pattern row are aligned in the second direction.

公开(公告)号：US20240381618A1

公开(公告)日：2024-11-14

申请号：US18637650

申请日：2024-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Kim ,  Myeongdong Lee ,  Seungbo Ko ,  Donghyuk Ahn

IPC: H10B12/00

Abstract: A semiconductor device includes a first contact structure on a central portion of the active pattern, a bit line structure on the first contact structure, a spacer structure on sidewalls of the bit line structure and the first contact structure and including a first spacer, a second spacer, an etch stop pattern and a third spacer sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate, a second contact structure on an end portion of the active pattern, and a capacitor on the second contact structure. A lowermost surface of the first spacer may be lower than a lowermost surface of the second spacer, and lower surfaces of the etch stop pattern and the third spacer may be higher than the lowermost surface of the second spacer.

公开(公告)号：US11980025B2

公开(公告)日：2024-05-07

申请号：US17705991

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok Ahn ,  Huijung Kim ,  Kiseok Lee ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes; an active region defined by an isolation film on a substrate, a word line in the substrate, the word line extending in a first direction and crossing the active region, a bit line above the word line and extending in a second direction, a contact between bit lines adjacent in the first direction, the contact connecting the active region and extending in a vertical direction, and a contact fence disposed on each of opposing side surfaces of the contact in the second direction and extending in the vertical direction, wherein the active region has a bar shape extending oblique to the first direction, and the contact fence includes a carbon-containing insulating film.

公开(公告)号：US20240306374A1

公开(公告)日：2024-09-12

申请号：US18414655

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUNNAM KIM ,  Seungbo Ko ,  Jongmin Kim ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.

公开(公告)号：US20220336465A1

公开(公告)日：2022-10-20

申请号：US17667195

申请日：2022-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

IPC: H01L27/108 ,  H01L23/528

Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.