知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.013 seconds)

    SEMICONDUCTOR DEVICES
    2.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240315006A1

    公开(公告)日：2024-09-19

    申请号：US18424447

    申请日：2024-01-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Junhyeok Ahn ,  Chansic Yoon ,  Myeongdong Lee

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

    Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate, a first contact structure on a central portion of each active pattern, a bit line structure on the first contact structure, a second contact structure on an end portion of each active pattern, a third contact structure on the second contact structure, a filling pattern between the bit line structure and the third contact structure and including a void, and a capacitor electrically connected to the third contact structure. The active pattern array includes active pattern rows spaced apart from each other in a first direction, and each active pattern row includes the active patterns spaced apart from each other in a second direction. Each active pattern extends in a third direction, and the active patterns in each active pattern row are aligned in the second direction.

    SEMICONDUCTOR DEVICES
    4.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240306374A1

    公开(公告)日：2024-09-12

    申请号：US18414655

    申请日：2024-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KEUNNAM KIM ,  Seungbo Ko ,  Jongmin Kim ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Myeongdong Lee

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

    Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.

Patent Agency Ranking