公开(公告)号：US11462610B2

公开(公告)日：2022-10-04

申请号：US16947090

申请日：2020-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Choi ,  Byunghyun Lee ,  Byeongjoo Ku ,  Seungjin Kim ,  Sangjae Park ,  Jinwoo Bae ,  Hangeol Lee ,  Bowo Choi ,  Hyunsil Hong

IPC: H01L27/108 ,  H01L49/02

Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.

公开(公告)号：US12193210B2

公开(公告)日：2025-01-07

申请号：US17719622

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Lee ,  Kijeong Kim ,  Jongcheon Kim ,  Donghwi Shin ,  Hyunsil Hong

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: In a method of forming a wiring, an insulating interlayer including a low-k dielectric material is formed on a substrate. A first etching mask is formed on the insulating interlayer. A first etching process is performed using the first etching mask to form a first opening through the insulating interlayer. The first etching mask is removed. A protection pattern is formed on a bottom and a side of the first opening. A second etching mask is formed on the protection pattern and the insulating interlayer. A second etching process is performed using a second etching mask to form a second opening through the insulating interlayer. The second etching mask is removed. The protection pattern is removed. A wiring is formed in each of the first and second openings.