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公开(公告)号：US11811364B2
公开(公告)日：2023-11-07
申请号：US17845378
申请日：2022-06-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehong Jung , Seunghyun Oh , Jinhyeon Lee , Gihyeok Ha , Seungjin Kim , Joomyoung Kim , Yelim Youn , Jaehoon Lee
CPC classification number: H03B5/32 , G06F1/06 , H03B5/04 , H03B5/20 , H03B2200/0082
Abstract: A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.
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2.发明授权公开(公告)号：US11777510B2
公开(公告)日：2023-10-03
申请号：US17964377
申请日：2022-10-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Baekmin Lim , Seungjin Kim , Seunghyun Oh
CPC classification number: H03L7/1976 , H03L7/081 , H03L7/093
Abstract: A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.
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公开(公告)号：US11435780B2
公开(公告)日：2022-09-06
申请号：US16743656
申请日：2020-01-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungjun Lee , Seungjin Kim , Jiyong Kim , Jungchul An , Joungmin Cho , Kwangtai Kim , Donghyun Yeom
IPC: G06F1/16 , G09G3/20 , H04N13/106
Abstract: In an electronic device and a method for operating the electronic device according to various embodiments, an electronic device may include a foldable housing including a hinge, a first housing connected to the hinge, and a second housing connected to the hinge and configured to be foldable with the first housing about the hinge, a display including a bent area in a state in which the first housing and the second housing are folded with respect to each other, a processor disposed in the first housing or the second housing and operatively connected to the display, and a memory operatively connected to the processor, and the memory may be configured to store instructions that, when executed, cause the processor to control the electronic device to: identify a folding degree between the first housing and the second housing, generate a first image based on mapping data in which the folding degree and characteristics of the first image are mapped, generate a synthetic image of the first image and a second image corresponding to the bent area wherein the generated first image is overlaid in at least a partial area of the second image, and display the generated synthetic image.
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公开(公告)号：US11004428B2
公开(公告)日：2021-05-11
申请号：US16558904
申请日：2019-09-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungjin Kim , Joonyung Park , Kwangrae Cho
Abstract: Disclosed is an electronic device that includes a display, a memory, and a processor configured to combine a plurality of images based on an execution of a plurality of applications so that the plurality of images is displayed in a single screen form, identify coordinate information of a display area of each of a first image and a second image on the screen based on the first image and second image belonging to the plurality of images and being updated, store the first image and the second image in a contiguous address of the memory, and transmit the coordinate information of the display area of each of the first image and the second image and the stored first image and second image to the display.
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公开(公告)号：US10804907B2
公开(公告)日：2020-10-13
申请号：US16290067
申请日：2019-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungjin Kim , Jihyun Kim , Taeik Kim
Abstract: A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.
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Patent Agency Ranking
公开(公告)号：US11862125B2
公开(公告)日：2024-01-02
申请号：US18104965
申请日：2023-02-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gwanghui Lee , Minwoo Lee , Minwoo Kim , Seungjin Kim , Woojun Jung
CPC classification number: G09G5/12 , G09G2320/0626 , G09G2340/0435
Abstract: On an electronic device which includes a display device comprising a display driving circuit, a processor, and a memory a method for changing a refresh rate of the display device includes: changing at least one of a first parameter, a second parameter, or a third parameter in response to identifying the occurrence of at least one of a scan rate change request or a change in scan rate change restriction, and applying the changed parameter among the first parameter, the second parameter, and the third parameter. The first parameter is the frequency of a first synchronization signal generated in the display driving circuit, the second parameter is the increase or decrease in a blank area to substitute for a portion of active video area in frame information, and the third parameter is the frequency of a second synchronization signal for rendering.
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公开(公告)号：US11616118B2
公开(公告)日：2023-03-28
申请号：US16938286
申请日：2020-07-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungjin Kim , Sungsoo Yim , Suklae Kim , Hyukwoo Kwon , Byunghyun Lee , Yoonyoung Choi
IPC: H01L49/02 , H01L27/108
Abstract: An integrated circuit semiconductor device includes a plurality of cylindrical structures separated from each other on a substrate; and a plurality of supporters having an opening region exposing side surfaces of the plurality of cylindrical structures, the plurality of supporters being in contact with the side surfaces of the plurality of cylindrical structures and supporting the plurality of cylindrical structures, wherein each of the plurality of supporters has both side surfaces having slopes and has a top width that is less than a bottom width.
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公开(公告)号：US11328661B2
公开(公告)日：2022-05-10
申请号：US17161800
申请日：2021-01-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gwanghui Lee , Seungjin Kim , Minwoo Kim , Seoyoung Lee , Woojun Jung
IPC: G09G5/18 , G09G3/3225
Abstract: In accordance with certain embodiments, an electronic device comprises: a memory; a display; and a processor operatively connected with the memory, wherein the processor is configured to: identify a target refresh rate and a current refresh rate of the display; and change the refresh rate of the display to a first refresh rate between the current refresh rate and the target refresh rate before changing the refresh rate of the display to the target refresh rate.
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公开(公告)号：US10256826B2
公开(公告)日：2019-04-09
申请号：US15229499
申请日：2016-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungjin Kim , Jihyun Kim , Taeik Kim
IPC: H04B1/69 , B32B3/18 , H03L7/08 , G06F1/08 , H03B1/00 , H03D3/24 , B32B3/26 , H03L7/00 , G06F1/10 , H02M3/07 , H03K5/26 , H03L7/093 , H03L7/099
Abstract: A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.
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公开(公告)号：US20250140144A1
公开(公告)日：2025-05-01
申请号：US19009676
申请日：2025-01-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungbae KIM , Euntaik Lee , Hyeonsu Lee , Seungjin Kim , Jinwoong Seok , Mooyoung Kim , Boyeon Na
Abstract: An electronic device for reducing a screen providing time and a control method thereof are provided. The electronic device includes a processor, a memory configured to store instructions, a display module configured to be driven in at least one state of a first state or a second state, wherein the second state is different from the first state, and a sensor module configured to detect the state of the display module, wherein, the instructions, when executed by the processor, cause the electronic device to determine whether the display module changes from the first state to the second state, in response to the state of the display module changing to the second state, generate image information obtained by converting an image displayed on the display module in the first state, store the generated image information in the at least one memory, and in response to the display module changing from the second state to the first state, output an image displayed on the display module based on the stored image information. The image information obtained by converting the image displayed on the display module may include information on an image converted from an image desired by a user.
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