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公开(公告)号：US12192525B2
公开(公告)日：2025-01-07
申请号：US18352796
申请日：2023-07-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehong Jung , Juhyung Son , Dongcheol Kim , Geonjung Ko , Jinsam Kwak
IPC: H04N19/176 , H04N19/12 , H04N19/61 , H04N19/625
Abstract: A video signal processor is configured to: obtain at least one transform block for a residual signal of a current block from a video signal bitstream, wherein the transform block comprises a plurality of transform coefficients two-dimensionally arranged, determine, on the basis of length information of a first side of the transform block, a horizontal transform kernel for horizontal transformation of the transform block, regardless of a length of a second side of the transform block, which is orthogonal to the first side, determine, on the basis of length information of the second side, a vertical transform kernel for vertical transformation of the transform block, regardless of a length of the first side, obtain the residual signal of the current block by performing, on the transform block, inverse transformation using the horizontal transform kernel and the vertical transform kernel, and reconstruct the current block based on the residual signal.
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公开(公告)号：US12149742B2
公开(公告)日：2024-11-19
申请号：US18341983
申请日：2023-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehong Jung , Juhyung Son , Dongcheol Kim , Geonjung Ko , Jinsam Kwak
IPC: H04N19/61 , H04N19/132 , H04N19/176 , H04N19/18 , H04N19/70
Abstract: A video signal decoding apparatus, comprising a processor, wherein the processor is configured to: parse a syntax element related to a secondary transform of a coding unit based on whether a prediction method of the coding unit is MIP (Matrix based Intra Prediction), check whether or not the secondary transform is applied to a transform block included in the coding unit based on the parsed syntax element, obtain one or more inverse transform coefficients based on an inverse transform of the secondary transform when the secondary transform is applied to the transform block, obtain a residual sample for the transform block based on the one or more inverse transform coefficients.
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公开(公告)号：US11368125B2
公开(公告)日：2022-06-21
申请号：US17340593
申请日：2021-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehong Jung , Wonkang Kim , Seungjin Kim , Seunghyun Oh
Abstract: A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.
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公开(公告)号：US11956424B2
公开(公告)日：2024-04-09
申请号：US18146642
申请日：2022-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Geonjung Ko , Dongcheol Kim , Juhyung Son , Jaehong Jung , Jinsam Kwak
IPC: H04N19/105 , H04N19/132 , H04N19/159 , H04N19/176 , H04N19/46 , H04N19/82
CPC classification number: H04N19/105 , H04N19/132 , H04N19/159 , H04N19/176 , H04N19/46 , H04N19/82
Abstract: A video signal processing method comprises: a step for deriving an intra prediction mode of a current block; a step for constructing a reference sample around the current block; a step for generating a prediction sample of the current block by using the reference sample on the basis of the intra prediction mode; and a step for restoring the current block on the basis of the prediction sample. The step for generating the prediction sample may comprise: a step for setting a filter flag value which specifies a filter coefficient of an interpolation filter applied to the reference sample on the basis of the width and height of the current block; and a step for performing filtering on the reference sample by using the interpolation filter having the filter coefficient specified by the filter flag.
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5.发明授权公开(公告)号：US11943378B2
公开(公告)日：2024-03-26
申请号：US18136447
申请日：2023-04-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehong Jung , Gyeongtae Kim , Yongseok Lee , Jinman Kim , Souksu Jang , Hyeyeong Choi , Jiwoo Lee
CPC classification number: H04M1/0264 , G03B17/561 , H04N23/51
Abstract: An electronic device is disclosed herein. The device includes a housing including a first opening formed in a surface thereof, a camera at least partially disposed in the housing, such that a lens of the camera is aligned with the first opening, a camera bracket including a flange structure disposed in the housing and spaced apart from the surface of the housing at a predetermined interval, a protruding structure extending from the flange structure into a space defined between the camera and an inner wall of the first opening to surround at least part of the camera, wherein the flange structure includes a first through-hole, and the protruding structure includes a recess, and wherein the protruding structure and the inner wall of the first opening form a microphone hole in communication with the recess and part of the first opening, an adhesive member disposed between the flange structure and an inner surface of the housing, the adhesive member including a passage, wherein one side of the passage is connected to the recess, and an opposite side of the passage is connected to the first through-hole, and a microphone element disposed in the housing and aligned with the first through-hole.
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Patent Agency Ranking
公开(公告)号：US11863760B2
公开(公告)日：2024-01-02
申请号：US17875411
申请日：2022-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongcheol Kim , Geonjung Ko , Jaehong Jung , Juhyung Son , Jinsam Kwak
IPC: H04N19/105 , H04N19/11 , H04N19/176 , H04N19/593 , H04N19/159 , H04N19/117 , H04N19/124 , H04N19/13
CPC classification number: H04N19/159 , H04N19/105 , H04N19/11 , H04N19/176 , H04N19/593 , H04N19/117 , H04N19/124 , H04N19/13
Abstract: Disclosed is a video signal processing method and device for encoding or decoding a video signal. More specifically, disclosed are a video signal processing method and a video signal processing device for performing the method, the method comprising: obtaining reference line information indicating a reference line for intra prediction of a current block among a plurality of reference lines comprising neighboring samples of the current block; determining, on the basis of the reference line information, an intra prediction mode for the current block among a plurality of intra prediction modes constituting an intra prediction mode set; and decoding the current block on the basis of a plurality of reference samples on the reference line according to the reference line information and the determined intra prediction mode.
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7.发明授权公开(公告)号：US11641415B2
公开(公告)日：2023-05-02
申请号：US17872101
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehong Jung , Gyeongtae Kim , Yongseok Lee , Jinman Kim , Souksu Jang , Hyeyeong Choi , Jiwoo Lee
Abstract: An electronic device is disclosed herein. The device includes a housing including a first opening formed in a surface thereof, a camera at least partially disposed in the housing, such that a lens of the camera is aligned with the first opening, a camera bracket including a flange structure disposed in the housing and spaced apart from the surface of the housing at a predetermined interval, a protruding structure extending from the flange structure into a space defined between the camera and an inner wall of the first opening to surround at least part of the camera, wherein the flange structure includes a first through-hole, and the protruding structure includes a recess, and wherein the protruding structure and the inner wall of the first opening form a microphone hole in communication with the recess and part of the first opening, an adhesive member disposed between the flange structure and an inner surface of the housing, the adhesive member including a passage, wherein one side of the passage is connected to the recess, and an opposite side of the passage is connected to the first through-hole, and a microphone element disposed in the housing and aligned with the first through-hole.
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公开(公告)号：US11057040B2
公开(公告)日：2021-07-06
申请号：US17006152
申请日：2020-08-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehong Jung , Sangdon Jung , Kyungmin Lee , Byungki Han
Abstract: A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.
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公开(公告)号：US10483985B2
公开(公告)日：2019-11-19
申请号：US15834342
申请日：2017-12-07
Inventor： Chisung Bae , Sangjoon Kim , Yoonmyung Lee , Jaehong Jung , Jung-Hoon Chun
Abstract: An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.
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公开(公告)号：US12219176B2
公开(公告)日：2025-02-04
申请号：US18352775
申请日：2023-07-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehong Jung , Juhyung Son , Dongcheol Kim , Geonjung Ko , Jinsam Kwak
IPC: H04N19/176 , H04N19/12 , H04N19/61 , H04N19/625
Abstract: A video signal processor is configured to: obtain at least one transform block for a residual signal of a current block from a video signal bitstream, wherein the transform block comprises a plurality of transform coefficients two-dimensionally arranged, determine, on the basis of length information of a first side of the transform block, a horizontal transform kernel for horizontal transformation of the transform block, regardless of a length of a second side of the transform block, which is orthogonal to the first side, determine, on the basis of length information of the second side, a vertical transform kernel for vertical transformation of the transform block, regardless of a length of the first side, obtain the residual signal of the current block by performing, on the transform block, inverse transformation using the horizontal transform kernel and the vertical transform kernel, and reconstruct the current block based on the residual signal.
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