公开(公告)号：US11777510B2

公开(公告)日：2023-10-03

申请号：US17964377

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baekmin Lim ,  Seungjin Kim ,  Seunghyun Oh

IPC: H03L7/197 ,  H03L7/093 ,  H03L7/081

CPC classification number: H03L7/1976 ,  H03L7/081 ,  H03L7/093

Abstract: A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

公开(公告)号：US11496137B2

公开(公告)日：2022-11-08

申请号：US17536514

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baekmin Lim ,  Seungjin Kim

IPC: H03L7/095 ,  H03L7/099 ,  H03L7/089 ,  H03M7/16

Abstract: An automatic frequency calibration and lock detection circuit includes a frequency error generator circuit, an automatic frequency calibration signal generator circuit, and a lock flag generator circuit. The frequency error generator circuit generates a frequency error signal based on a reference frequency signal and an output frequency signal. The frequency error signal represents a difference between a frequency of the output frequency signal and a target frequency. The automatic frequency calibration signal generator circuit generates an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal. The lock flag generator circuit generates a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal. The frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.