公开(公告)号：US12193210B2

公开(公告)日：2025-01-07

申请号：US17719622

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Lee ,  Kijeong Kim ,  Jongcheon Kim ,  Donghwi Shin ,  Hyunsil Hong

IPC: H10B12/00 ,  H01L21/027 ,  H01L21/311

Abstract: In a method of forming a wiring, an insulating interlayer including a low-k dielectric material is formed on a substrate. A first etching mask is formed on the insulating interlayer. A first etching process is performed using the first etching mask to form a first opening through the insulating interlayer. The first etching mask is removed. A protection pattern is formed on a bottom and a side of the first opening. A second etching mask is formed on the protection pattern and the insulating interlayer. A second etching process is performed using a second etching mask to form a second opening through the insulating interlayer. The second etching mask is removed. The protection pattern is removed. A wiring is formed in each of the first and second openings.