公开(公告)号：US20240381618A1

公开(公告)日：2024-11-14

申请号：US18637650

申请日：2024-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Kim ,  Myeongdong Lee ,  Seungbo Ko ,  Donghyuk Ahn

IPC: H10B12/00

Abstract: A semiconductor device includes a first contact structure on a central portion of the active pattern, a bit line structure on the first contact structure, a spacer structure on sidewalls of the bit line structure and the first contact structure and including a first spacer, a second spacer, an etch stop pattern and a third spacer sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate, a second contact structure on an end portion of the active pattern, and a capacitor on the second contact structure. A lowermost surface of the first spacer may be lower than a lowermost surface of the second spacer, and lower surfaces of the etch stop pattern and the third spacer may be higher than the lowermost surface of the second spacer.

公开(公告)号：US20230422488A1

公开(公告)日：2023-12-28

申请号：US18192329

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Sohyun Park ,  Chansic Yoon ,  Dongmin Choi ,  Seungbo Ko ,  Hyosub Kim ,  Jingkuk Bae ,  Woojin Jeong ,  Eunkyung Cha ,  Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/315

Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.

公开(公告)号：US20250120073A1

公开(公告)日：2025-04-10

申请号：US18906420

申请日：2024-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghoon Bae ,  Seungbo Ko ,  Euna Kim

IPC: H10B12/00

Abstract: Provided is an integrated circuit device including a substrate having a cell array area, a peripheral circuit area surrounding the cell array area, and an interface area between the cell array area and the peripheral circuit area, a plurality of bit lines extending in a first horizontal direction on the cell array area and the interface area and placed parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, insulating capping patterns extending in the first horizontal direction on the bit lines, a plurality of contact plugs vertically connected to the bit lines, respectively, in the interface area, and a plurality of contact pads disposed on the plurality of contact plugs, respectively, wherein the contact plugs are spaced apart from centers of the bit lines in the second horizontal direction at a certain gap in the second horizontal direction.

公开(公告)号：US20240306374A1

公开(公告)日：2024-09-12

申请号：US18414655

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KEUNNAM KIM ,  Seungbo Ko ,  Jongmin Kim ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Chansic Yoon ,  Kiseok Lee ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes an active pattern array including active patterns, an isolation pattern, gate structures, bit line structures, and lower and upper contact plugs. The isolation pattern covers sidewalls of the active patterns. The gate structures extend through upper portions of the active patterns and the isolation pattern in a first direction, and are spaced apart from each other in a second direction. The bit line structures are on central portions of the active patterns and the isolation pattern, extend in the second direction, and are spaced apart from each other in the first direction. The lower contact plugs are disposed on end portions of the active patterns. The upper contact plugs are disposed on the lower contact plugs. The active pattern array includes active pattern rows including the active patterns spaced apart from each other in the first direction.