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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权

    公开(公告)号：US20210351184A1

    公开(公告)日：2021-11-11

    申请号：US17384347

    申请日：2021-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

    Semiconductor devices
    2.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US12289881B2

    公开(公告)日：2025-04-29

    申请号：US17948796

    申请日：2022-09-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongmin Kim ,  Chansic Yoon ,  Hyosub Kim ,  Sohyun Park ,  Junhyeok Ahn

    IPC: H10B12/00 ,  H10D64/23

    Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

    SEMICONDUCTOR DEVICES
    3.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230422488A1

    公开(公告)日：2023-12-28

    申请号：US18192329

    申请日：2023-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin KIM ,  Sohyun Park ,  Chansic Yoon ,  Dongmin Choi ,  Seungbo Ko ,  Hyosub Kim ,  Jingkuk Bae ,  Woojin Jeong ,  Eunkyung Cha ,  Junhyeok Ahn

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/315

    Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.

    Semiconductor devices
    4.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11706910B2

    公开(公告)日：2023-07-18

    申请号：US17229942

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Manbok Kim ,  Soojeong Kim ,  Chulkwon Park ,  Seungbae Jeon ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482

    Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

    Semiconductor device and manufacturing method of the same
    5.
    发明授权
    Semiconductor device and manufacturing method of the same 有权

    公开(公告)号：US11616066B2

    公开(公告)日：2023-03-28

    申请号：US17384347

    申请日：2021-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

    Semiconductor and manufacturing method of the same
    6.
    发明授权
    Semiconductor and manufacturing method of the same 有权

    公开(公告)号：US11088143B2

    公开(公告)日：2021-08-10

    申请号：US16896470

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

    SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME
    9.
    发明申请
    SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME 有权

    公开(公告)号：US20210066305A1

    公开(公告)日：2021-03-04

    申请号：US16896470

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

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