公开(公告)号：US20240260256A1

公开(公告)日：2024-08-01

申请号：US18424919

申请日：2024-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyoung EOM ,  Sunghoon Bae ,  Halim Noh ,  Heecheol Shin

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/033 ,  H10B12/315 ,  H10B12/50

Abstract: A semiconductor device includes a substrate having an active region defined by a device separation layer, a plurality of bit lines on the substrate, a buried contact disposed on the substrate between adjacent bit lines among the plurality of bit lines and connected to the active region, an intermediate conductive layer disposed on the buried contact, a landing pad disposed on the intermediate conductive layer, and an insulating pattern on a sidewall of the landing pad and contacting at least a portion of a top surface of the intermediate conductive layer.

公开(公告)号：US20250120073A1

公开(公告)日：2025-04-10

申请号：US18906420

申请日：2024-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghoon Bae ,  Seungbo Ko ,  Euna Kim

IPC: H10B12/00

Abstract: Provided is an integrated circuit device including a substrate having a cell array area, a peripheral circuit area surrounding the cell array area, and an interface area between the cell array area and the peripheral circuit area, a plurality of bit lines extending in a first horizontal direction on the cell array area and the interface area and placed parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, insulating capping patterns extending in the first horizontal direction on the bit lines, a plurality of contact plugs vertically connected to the bit lines, respectively, in the interface area, and a plurality of contact pads disposed on the plurality of contact plugs, respectively, wherein the contact plugs are spaced apart from centers of the bit lines in the second horizontal direction at a certain gap in the second horizontal direction.