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公开(公告)号：US12200866B2
公开(公告)日：2025-01-14
申请号：US17860781
申请日：2022-07-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyonghwan Cho , Jongmin Kim , Youngjung Kim , Sangho Hong
Abstract: An electronic device may include a printed circuit board including a connector configured to move between a first position and a second position on the printed circuit board; an antenna; a support member that is disposed between the printed circuit board and the antenna in a direction in which the printed circuit board, the support member, and the antenna are stacked; a signal connection member that is electrically connected to the connector of the printed circuit board; and a conductive member disposed between the printed circuit board and the support member, and aligned to cover the first position and the second position of the printed circuit board.
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公开(公告)号：US20240349491A1
公开(公告)日：2024-10-17
申请号：US18534400
申请日：2023-12-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myeong-Dong Lee , Jongmin Kim , Taejin Park , Seung-Bo Ko , Hui-Jung Kim
IPC: H10B12/00
CPC classification number: H10B12/485 , H10B12/482 , H10B12/488
Abstract: An example semiconductor memory device includes first and second active patterns, which are extended in a first direction and are disposed side by side in a second direction. Each of the first and second active patterns includes first and second edge portions, which are spaced apart from each other in the first direction. A pair of word lines are disposed to cross each of the first and second active patterns, a pair of bit lines are disposed on each of the first and second active patterns and are extended in a third direction, and a storage node contacts on the first edge portion of the first active pattern. When measured in the second direction, a first width of the storage node contact at a first level is larger than a second width at a second level. The first level is lower than the second level.
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公开(公告)号：US20230185470A1
公开(公告)日：2023-06-15
申请号：US17868147
申请日：2022-07-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyungjune Cho , Jongmin Kim , Minsik Oh , Joohyeong Yoon , Keunhwan Lee , Youngjin Cho
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0616 , G06F3/0659 , G06F3/0679
Abstract: A memory system includes a memory controller and a memory device including a plurality of dies, each die including a plurality of blocks. A plurality of commands are configured to control the memory device in units of super blocks. During a first time interval, a first erase operation is performed on a first-first block among the first-first block to a first-Mth block, and a first program operation is performed on a second-first block to a second-Mth block, based on the first commands. During a second time interval, a second erase operation is performed on a first-second block among the first-first block to the first-Mth block, and a second program operation is performed on the first-first block and one or more blocks among the second-first block to the second-Mth block, based on the second commands.
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公开(公告)号：US20250016980A1
公开(公告)日：2025-01-09
申请号：US18629799
申请日：2024-04-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok Lee , Bongsoo Kim , Yongkwan Kim , Jongmin Kim , Taejin Park , Chansic Yoon , Jinwoo Han
IPC: H10B12/00
Abstract: A semiconductor device includes an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction and crossing central portions of the active patterns; a bit line structure contacting first portions of the active patterns adjacent to a first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction oblique with respect to the first direction. The active patterns arranged side by side in the second direction form an active column.
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公开(公告)号：US20240188284A1
公开(公告)日：2024-06-06
申请号：US18371663
申请日：2023-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongmin Kim , Chansic Yoon , Junhyeok Ahn
IPC: H10B12/00
CPC classification number: H10B12/482 , H10B12/02 , H10B12/315 , H10B12/485
Abstract: A semiconductor device includes a gate electrode disposed within a cell region of a substrate, each of bit line structure pairs including a first bit line structure and a second bit line structure, and extension portion pairs disposed within an interface region of the substrate, each extension portion pair including a first extension portion and a second extension portion that are connected to the first bit line structure and the second bit line structure, respectively. The bit line structure pairs are spaced apart from each other by a first distance. In each bit line structure pair, the first bit line structure and the second bit line structure are spaced apart from each other by the first distance. In each extension portion pair, the first extension portion and the second extension portion are spaced apart from each other at a second distance less than the first distance.
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Patent Agency Ranking
公开(公告)号：US11238954B2
公开(公告)日：2022-02-01
申请号：US16998068
申请日：2020-08-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongmin Kim , Yeongjin Seo , Keun-Hwan Lee
Abstract: A storage device includes a plurality of nonvolatile memory devices; and a controller connected in common to the plurality of nonvolatile memory devices through data lines, the controller being configured to detect first offset information by performing a first training operation with respect to a first nonvolatile memory device from among the plurality of nonvolatile memory devices, the controller being further configured to, based on the first offset information, perform a second training operation with respect to a second nonvolatile memory device from among the plurality of nonvolatile memory devices.
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公开(公告)号：US12289881B2
公开(公告)日：2025-04-29
申请号：US17948796
申请日：2022-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jongmin Kim , Chansic Yoon , Hyosub Kim , Sohyun Park , Junhyeok Ahn
Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.
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公开(公告)号：US20240431097A1
公开(公告)日：2024-12-26
申请号：US18545328
申请日：2023-12-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunjin Lee , Jongmin Kim , Kiseok Lee , Yun Choi , Inwoo Kim , Hui-Jung Kim , Sohyun Park , Heejae Chae
IPC: H10B12/00
Abstract: Disclosed is a semiconductor device comprising an active pattern including first and second edge parts spaced apart from each other in a first direction, a word line extending along a second direction between the first and second edge parts, a bit line extending along a third direction on the first edge part, a storage node contact on the second edge part, a first active pad between the bit line and the first edge part, and a second active pad between the storage node contact and the second edge part. The first active pad extends in the third direction more than the first edge part. The second active pad extends in a direction opposite to the third direction more than the second edge part.
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公开(公告)号：US12155115B2
公开(公告)日：2024-11-26
申请号：US17941366
申请日：2022-09-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghwan Hyun , Jaehyun Kwon , Jongmin Kim , Yangtack Oh , Seongeun Bae
Abstract: An electronic device is provided. The electronic device includes a housing, a circuit board disposed in the housing and receiving a communication module, an antenna assembly disposed in the housing and including an antenna pattern electrically connected with the communication module and a ground pattern, and a conductive plate disposed on the antenna assembly. At least a portion of the ground pattern may be positioned between the antenna pattern and the conductive plate. The conductive plate may be configured to be electrically coupled with the antenna pattern through the ground pattern.
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公开(公告)号：US20240381618A1
公开(公告)日：2024-11-14
申请号：US18637650
申请日：2024-04-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongmin Kim , Myeongdong Lee , Seungbo Ko , Donghyuk Ahn
IPC: H10B12/00
Abstract: A semiconductor device includes a first contact structure on a central portion of the active pattern, a bit line structure on the first contact structure, a spacer structure on sidewalls of the bit line structure and the first contact structure and including a first spacer, a second spacer, an etch stop pattern and a third spacer sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate, a second contact structure on an end portion of the active pattern, and a capacitor on the second contact structure. A lowermost surface of the first spacer may be lower than a lowermost surface of the second spacer, and lower surfaces of the etch stop pattern and the third spacer may be higher than the lowermost surface of the second spacer.
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