公开(公告)号：US11665883B2

公开(公告)日：2023-05-30

申请号：US17202465

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inkyoung Heo ,  Hyo-Sub Kim ,  Sohyun Park ,  Taejin Park ,  Seung-Heon Lee ,  Youn-Seok Choi ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768 ,  H01L23/482 ,  H01L21/762

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L23/5329 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L21/76264 ,  H01L23/4821

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

公开(公告)号：US12167587B2

公开(公告)日：2024-12-10

申请号：US17733051

申请日：2022-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun Lee ,  Suk Hoon Kim ,  Hyo-Sub Kim

IPC: H10B12/00

Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

公开(公告)号：US11600570B2

公开(公告)日：2023-03-07

申请号：US17097337

申请日：2020-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sub Kim ,  Sohyun Park ,  Daewon Kim ,  Dongoh Kim ,  Eun A Kim ,  Chulkwon Park ,  Taejin Park ,  Kiseok Lee ,  Sunghee Han

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

公开(公告)号：US11468919B2

公开(公告)日：2022-10-11

申请号：US16841850

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin Park ,  Won Seok Yoo ,  Keun Nam Kim ,  Hyo-Sub Kim ,  So Hyun Park ,  In Kyoung Heo ,  Yoo Sang Hwang

IPC: G11C5/06 ,  H01L27/108

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

公开(公告)号：US20210035613A1

公开(公告)日：2021-02-04

申请号：US16841850

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin PARK ,  Won Seok Yoo ,  Keun Nam Kim ,  Hyo-Sub Kim ,  So Hyun Park ,  In Kyoung Heo ,  Yoo Sang Hwang

IPC: G11C5/06 ,  H01L27/108

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.