公开(公告)号：US11665883B2

公开(公告)日：2023-05-30

申请号：US17202465

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inkyoung Heo ,  Hyo-Sub Kim ,  Sohyun Park ,  Taejin Park ,  Seung-Heon Lee ,  Youn-Seok Choi ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768 ,  H01L23/482 ,  H01L21/762

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L23/5329 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L21/76264 ,  H01L23/4821

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

公开(公告)号：US11282787B2

公开(公告)日：2022-03-22

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US11929324B2

公开(公告)日：2024-03-12

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  G11C5/10 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L29/0649 ,  H01L29/4236 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US11688779B2

公开(公告)日：2023-06-27

申请号：US17387427

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Junhyeok Ahn ,  Jae Hyun Yoon ,  Myeong-Dong Lee ,  Seok Hwan Lee ,  Sunghee Han ,  Inkyoung Heo

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/45 ,  H01L27/108

CPC classification number: H01L29/41775 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1606 ,  H01L27/10814 ,  H01L29/45

Abstract: A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof.

公开(公告)号：US11658117B2

公开(公告)日：2023-05-23

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L27/10888 ,  H01L29/0649 ,  H01L29/4236

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20220165657A1

公开(公告)日：2022-05-26

申请号：US17667866

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEJIN PARK ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  G11C5/10 ,  H01L29/423 ,  H01L27/108 ,  H01L21/768

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US20210082799A1

公开(公告)日：2021-03-18

申请号：US16879009

申请日：2020-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/768 ,  H01L29/423 ,  H01L27/108 ,  G11C5/10

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.