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公开(公告)号：US11183500B2
公开(公告)日：2021-11-23
申请号：US16826655
申请日：2020-03-23
发明人： Hoju Song , Seokhyun Kim , Youngjun Kim , Jinhyung Park , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC分类号： H01L27/108
摘要： A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.
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公开(公告)号：US20240155836A1
公开(公告)日：2024-05-09
申请号：US18492821
申请日：2023-10-24
发明人： Joonyoung Kang , Hoju Song , Kanguk Kim , Seokhyun Kim , Youngjun Kim , Jooncheol Kim , Jinwoong Kim , Hoin Ryu , Hyeran Lee
IPC分类号： H10B12/00
CPC分类号： H10B12/485 , H10B12/02 , H10B12/315 , H10B12/34 , H10B12/482
摘要： Semiconductor devices may include: a substrate including a plurality of active areas defined by a device isolation layer; a plurality of bit lines extending on the substrate in a first horizontal direction; a plurality of insulation fences that are spaced apart from each other in the first horizontal direction in a space between two adjacent bit lines among the plurality of bit lines on the substrate; a plurality of buried contacts that are between the adjacent two bit lines among the plurality of bit lines and are arranged alternately with the plurality of insulation fences along the first horizontal direction on the substrate, the plurality of buried contacts being connected to the plurality of active areas, respectively; and a plurality of insulating layer, each of which is between a respective one of the plurality of insulation fences and a respective one of the plurality of buried contacts.
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公开(公告)号：US20240049445A1
公开(公告)日：2024-02-08
申请号：US18355429
申请日：2023-07-20
发明人： Hoju Song , Eunjung Kim , Kihyung Nam , Jaehyung Park , Yunjae Lee
IPC分类号： H10B12/00
CPC分类号： H10B12/09 , H10B12/315 , H10B12/50
摘要： A method of manufacturing a semiconductor device may include forming word lines in word line trenches on a substrate, removing a portion of the substrate located between a pair of the word lines to form a direct contact hole, forming on an inner wall of the direct contact hole a sacrificial liner structure that includes a first liner, a sacrificial layer, and a second liner, forming a preliminary direct contact in the direct contact hole, removing the sacrificial layer, while leaving the first and second liners, to form an air space between the first and second liners, forming a bit line stack that covers an upper surface the air space on the preliminary direct contact, patterning the bit line stack to form bit lines, and removing side portions of the second liner and the preliminary direct contact in the direct contact hole to form a direct contact.
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公开(公告)号：US20220077152A1
公开(公告)日：2022-03-10
申请号：US17199740
申请日：2021-03-12
发明人： Dongkyun Lim , Youngsin Kim , Kijin Park , Hoju Song , Dongkwan Yang , Sangho Yun , Gyuhyun Lee , Jieun Lee , Seunguk Han , Yoongi Hong
IPC分类号： H01L27/108 , H01L29/49 , H01L29/78
摘要： A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.
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公开(公告)号：US11690213B2
公开(公告)日：2023-06-27
申请号：US17199740
申请日：2021-03-12
发明人： Dongkyun Lim , Youngsin Kim , Kijin Park , Hoju Song , Dongkwan Yang , Sangho Yun , Gyuhyun Lee , Jieun Lee , Seunguk Han , Yoongi Hong
CPC分类号： H10B12/315 , H01L29/4941 , H01L29/66484 , H01L29/7831 , H01L29/7833
摘要： A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.
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公开(公告)号：US20220254787A1
公开(公告)日：2022-08-11
申请号：US17667697
申请日：2022-02-09
发明人： Youngjun Kim , Seokhyun Kim , Jinhyung Park , Hoju Song , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC分类号： H01L27/108
摘要： A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
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公开(公告)号：US20210035983A1
公开(公告)日：2021-02-04
申请号：US16826655
申请日：2020-03-23
发明人： Hoju Song , Seokhyun Kim , Youngjun Kim , Jinhyung Park , Hyeran Lee , Bongsoo Kim , Sungwoo Kim
IPC分类号： H01L27/108
摘要： A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.
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公开(公告)号：US11968824B2
公开(公告)日：2024-04-23
申请号：US18137169
申请日：2023-04-20
发明人： Youngjun Kim , Seokhyun Kim , Jinhyung Park , Hoju Song , Hyeran Lee , Sungwoo Kim , Bongsoo Kim
IPC分类号： H01L27/10 , H01L21/768 , H10B12/00
CPC分类号： H10B12/485 , H01L21/76829 , H10B12/0335 , H10B12/09 , H10B12/315
摘要： A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
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公开(公告)号：US20240130115A1
公开(公告)日：2024-04-18
申请号：US18367183
申请日：2023-09-12
发明人： Hoju Song
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/02 , H10B12/315 , H10B12/36
摘要： An integrated circuit (IC) device is provided. The IC device includes: a substrate having active regions; word lines extending in a first horizontal direction across the active regions; conductive expanded pads on the substrate and connected to the active regions; pad isolation structures located between the conductive expanded pads; direct contacts connected to the active regions; bit lines extending in a second horizontal direction perpendicular to the first horizontal direction, on the direct contacts and the pad isolation structures, and connected to the direct contacts; conductive plugs extending in a vertical direction on the conductive expanded pads and connected to the conductive expanded pads; and separation fences passing through the conductive expanded pads and the conductive plugs, and having sidewalls extending linearly in the vertical direction.
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公开(公告)号：US20240081045A1
公开(公告)日：2024-03-07
申请号：US18140004
申请日：2023-04-27
发明人： Jaehyung Park , Hoju Song , Eunjung Kim , Kihyung Nam , Yunjae Lee
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/315
摘要： A semiconductor device includes a substrate including a first region and a second region, a bit line structure that extends over the first region and the second region, an upper spacer structure on a first sidewall of the bit line structure on the first region of the substrate, and an insulation spacer structure on the first sidewall of the bit line structure on the second region of the bit line structure. The upper spacer structure may include first, second and third upper spacers sequentially stacked on the sidewall of the bit line structure in a first horizontal direction. The insulation spacer structure may include first, second, third and fourth insulation spacers sequentially stacked on the sidewall of the bit line structure in the first horizontal direction. The first, second and third insulation spacers include substantially the same materials as the first, second and third upper spacers, respectively.
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