公开(公告)号：US20240155836A1

公开(公告)日：2024-05-09

申请号：US18492821

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kang ,  Hoju Song ,  Kanguk Kim ,  Seokhyun Kim ,  Youngjun Kim ,  Jooncheol Kim ,  Jinwoong Kim ,  Hoin Ryu ,  Hyeran Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: Semiconductor devices may include: a substrate including a plurality of active areas defined by a device isolation layer; a plurality of bit lines extending on the substrate in a first horizontal direction; a plurality of insulation fences that are spaced apart from each other in the first horizontal direction in a space between two adjacent bit lines among the plurality of bit lines on the substrate; a plurality of buried contacts that are between the adjacent two bit lines among the plurality of bit lines and are arranged alternately with the plurality of insulation fences along the first horizontal direction on the substrate, the plurality of buried contacts being connected to the plurality of active areas, respectively; and a plurality of insulating layer, each of which is between a respective one of the plurality of insulation fences and a respective one of the plurality of buried contacts.

公开(公告)号：US11876043B2

公开(公告)日：2024-01-16

申请号：US16865544

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooncheol Kim ,  Sangwoo Hong

IPC: H01L23/522 ,  H01L23/544 ,  H01L23/528 ,  H01L21/66 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L23/5226 ,  H01L22/32 ,  H01L23/528 ,  H01L23/5223 ,  H01L23/53295 ,  H01L23/544 ,  H01L21/31144 ,  H01L21/32139 ,  H01L2223/5446

Abstract: A semiconductor device includes a substrate having a chip region and a scribe lane region having first edges extending in a first direction and second edges extending in a second direction, a first insulating interlayer structure on the scribe lane region and including a low-k dielectric material, first conductive structures on a portion of the scribe lane region adjacent one of the first edges and each extending through the first insulating interlayer structure in a vertical direction and extending in the first direction, a second insulating interlayer on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure, first vias each extending in the first direction through the second insulating interlayer to contact one of the first conductive structures, and a first wiring commonly contacting upper surfaces of the first vias.

公开(公告)号：US20240147702A1

公开(公告)日：2024-05-02

申请号：US18244456

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooncheol Kim ,  Kanguk Kim

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/34 ,  H10B12/50

Abstract: A semiconductor device includes a substrate including a cell region and a core/peripheral region, a bit line structure disposed on the substrate of the cell region and including a polysilicon structure, a barrier pattern, a metal pattern and a capping pattern that are stacked on each other, and a gate structure on the substrate of the core/peripheral region, the gate structure including a gate insulation pattern, a polysilicon pattern, a carbon-containing pattern, a barrier structure, a metal pattern and a capping pattern that are stacked on each other.

公开(公告)号：US20210082809A1

公开(公告)日：2021-03-18

申请号：US16865544

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooncheol Kim ,  Sangwoo HONG

IPC: H01L23/522 ,  H01L23/544 ,  H01L23/528 ,  H01L23/532 ,  H01L21/66

Abstract: A semiconductor device includes a substrate having a chip region and a scribe lane region having first edges extending in a first direction and second edges extending in a second direction, a first insulating interlayer structure on the scribe lane region and including a low-k dielectric material, first conductive structures on a portion of the scribe lane region adjacent one of the first edges and each extending through the first insulating interlayer structure in a vertical direction and extending in the first direction, a second insulating interlayer on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure, first vias each extending in the first direction through the second insulating interlayer to contact one of the first conductive structures, and a first wiring commonly contacting upper surfaces of the first vias.