公开(公告)号：US20240155836A1

公开(公告)日：2024-05-09

申请号：US18492821

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kang ,  Hoju Song ,  Kanguk Kim ,  Seokhyun Kim ,  Youngjun Kim ,  Jooncheol Kim ,  Jinwoong Kim ,  Hoin Ryu ,  Hyeran Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: Semiconductor devices may include: a substrate including a plurality of active areas defined by a device isolation layer; a plurality of bit lines extending on the substrate in a first horizontal direction; a plurality of insulation fences that are spaced apart from each other in the first horizontal direction in a space between two adjacent bit lines among the plurality of bit lines on the substrate; a plurality of buried contacts that are between the adjacent two bit lines among the plurality of bit lines and are arranged alternately with the plurality of insulation fences along the first horizontal direction on the substrate, the plurality of buried contacts being connected to the plurality of active areas, respectively; and a plurality of insulating layer, each of which is between a respective one of the plurality of insulation fences and a respective one of the plurality of buried contacts.

公开(公告)号：US20240147702A1

公开(公告)日：2024-05-02

申请号：US18244456

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooncheol Kim ,  Kanguk Kim

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/34 ,  H10B12/50

Abstract: A semiconductor device includes a substrate including a cell region and a core/peripheral region, a bit line structure disposed on the substrate of the cell region and including a polysilicon structure, a barrier pattern, a metal pattern and a capping pattern that are stacked on each other, and a gate structure on the substrate of the core/peripheral region, the gate structure including a gate insulation pattern, a polysilicon pattern, a carbon-containing pattern, a barrier structure, a metal pattern and a capping pattern that are stacked on each other.

公开(公告)号：US12022645B2

公开(公告)日：2024-06-25

申请号：US17398136

申请日：2021-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC: H10B12/00

CPC classification number: H10B12/0335 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/50

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US20240407150A1

公开(公告)日：2024-12-05

申请号：US18737605

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwa Jang ,  Kanguk Kim ,  Hyunsuk Noh ,  Yeongshin Park ,  Sangkyu Sun ,  Sunyoung Lee ,  Sohyang Lee ,  Hongjun Lee ,  Hosun Jung ,  Jeongmin Jin ,  Jeonghee Choi ,  Jinseo Choi ,  Cera Hong

IPC: H10B12/00

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.

公开(公告)号：US20240266170A1

公开(公告)日：2024-08-08

申请号：US18500662

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghwan Lee ,  Kanguk Kim ,  Seokhyun Kim ,  Wonchul Lee

IPC: H01L21/027 ,  H01L21/308 ,  H10B12/00

CPC classification number: H01L21/0276 ,  H01L21/3081 ,  H01L21/3086 ,  H10B12/09

Abstract: A method of forming a pattern includes forming an etch target layer over a substrate including a first area and a second area, forming a hardmask structure over the etch target layer, forming a photoresist pattern including a first photoresist pattern including an engraved pattern located in the first area and a second photoresist pattern including an embossed pattern located in the second area, forming an upper hardmask pattern including a plurality of openings, forming a reversible hardmask pattern filling the plurality of openings in the first area, and forming a feature pattern including a first pattern located in the first area and a second pattern located in the second area, wherein the first pattern includes a plurality of island patterns and a dam structure planarly surrounding the plurality of island patterns.