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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190355727A1

    公开(公告)日：2019-11-21

    申请号：US16242127

    申请日：2019-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Keunnam Kim ,  Eun A Kim ,  Eunjung Kim ,  Jeongseop Shim

    IPC: H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423

    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.

    Methods for fabricating semiconductor devices
    4.
    发明授权
    Methods for fabricating semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US09287300B2

    公开(公告)日：2016-03-15

    申请号：US14569980

    申请日：2014-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Yong Kwan Kim ,  Jemin Park ,  Semyeong Jang ,  Sangyeon Han ,  Yoosang Hwang

    IPC: H01L21/311 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768

    CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

    Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

    Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。

    Semiconductor devices and methods of fabricating the same
    5.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US12262526B2

    公开(公告)日：2025-03-25

    申请号：US18540076

    申请日：2023-12-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyeon Ryu ,  Eunjung Kim

    IPC: H01L21/762 ,  H01L49/02 ,  H10B12/00

    Abstract: Disclosed are a semiconductor device and a method of fabricating the same. In the semiconductor device, a supporting pattern may be used to fix upper portions of active patterns, when a gap-filling process is performed to fill a region between active patterns, and thus, it may be possible to prevent or reduce the likelihood of the active patterns from being bent or fallen. Thus, it may be possible to reduce failure of the semiconductor device and/or to improve reliability of the semiconductor device.

    SEMICONDUCTOR DEVICES
    6.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240081045A1

    公开(公告)日：2024-03-07

    申请号：US18140004

    申请日：2023-04-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyung Park ,  Hoju Song ,  Eunjung Kim ,  Kihyung Nam ,  Yunjae Lee

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315

    Abstract: A semiconductor device includes a substrate including a first region and a second region, a bit line structure that extends over the first region and the second region, an upper spacer structure on a first sidewall of the bit line structure on the first region of the substrate, and an insulation spacer structure on the first sidewall of the bit line structure on the second region of the bit line structure. The upper spacer structure may include first, second and third upper spacers sequentially stacked on the sidewall of the bit line structure in a first horizontal direction. The insulation spacer structure may include first, second, third and fourth insulation spacers sequentially stacked on the sidewall of the bit line structure in the first horizontal direction. The first, second and third insulation spacers include substantially the same materials as the first, second and third upper spacers, respectively.

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10468350B2

    公开(公告)日：2019-11-05

    申请号：US15592860

    申请日：2017-05-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

    IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

    Semiconductor devices
    8.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11903187B2

    公开(公告)日：2024-02-13

    申请号：US17547306

    申请日：2021-12-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Hyewon Kim ,  Sei-Ryung Choi

    IPC: H01L21/762 ,  H10B12/00

    CPC classification number: H10B12/50 ,  H01L21/76229 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, cell active patterns on the cell region of the substrate, peripheral active patterns on the peripheral region of the substrate, a boundary insulating pattern disposed on the boundary region of the substrate and disposed between the cell active patterns and the peripheral active patterns, and a bumper pattern disposed on the cell region of the substrate and disposed between the boundary insulating pattern and the cell active patterns. A width of the bumper pattern in a first direction parallel to a top surface of the substrate is greater than a width of each of the cell active patterns in the first direction.

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    9.
    发明公开
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240049445A1

    公开(公告)日：2024-02-08

    申请号：US18355429

    申请日：2023-07-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoju Song ,  Eunjung Kim ,  Kihyung Nam ,  Jaehyung Park ,  Yunjae Lee

    IPC: H10B12/00

    CPC classification number: H10B12/09 ,  H10B12/315 ,  H10B12/50

    Abstract: A method of manufacturing a semiconductor device may include forming word lines in word line trenches on a substrate, removing a portion of the substrate located between a pair of the word lines to form a direct contact hole, forming on an inner wall of the direct contact hole a sacrificial liner structure that includes a first liner, a sacrificial layer, and a second liner, forming a preliminary direct contact in the direct contact hole, removing the sacrificial layer, while leaving the first and second liners, to form an air space between the first and second liners, forming a bit line stack that covers an upper surface the air space on the preliminary direct contact, patterning the bit line stack to form bit lines, and removing side portions of the second liner and the preliminary direct contact in the direct contact hole to form a direct contact.

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10978397B2

    公开(公告)日：2021-04-13

    申请号：US16707294

    申请日：2019-12-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

    IPC: H01L23/532 ,  H01L21/764 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528 ,  H01L27/24

    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

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