公开(公告)号：US11744063B2

公开(公告)日：2023-08-29

申请号：US17374624

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/71 ,  H01L21/28 ,  H01L29/792 ,  H01L21/8234 ,  H10B12/00

CPC classification number: H10B12/482 ,  H01L21/71 ,  H01L29/40114 ,  H01L29/7926 ,  H10B12/053 ,  H10B12/31 ,  H10B12/315 ,  H10B12/34 ,  H10B12/48 ,  H01L21/823475

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US20210343724A1

公开(公告)日：2021-11-04

申请号：US17374624

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/792 ,  H01L21/71 ,  H01L21/28

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US10269808B2

公开(公告)日：2019-04-23

申请号：US15584342

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L27/108

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US11776909B2

公开(公告)日：2023-10-03

申请号：US17205462

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L21/764 ,  H01L23/532 ,  H10B12/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/0335 ,  H01L23/5222 ,  H10B12/315 ,  H10B63/30 ,  H10B63/80

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US20230225114A1

公开(公告)日：2023-07-13

申请号：US18124043

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L21/8234 ,  H10B12/00 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/823468 ,  H01L21/76829 ,  H01L21/76838 ,  H01L29/6656 ,  H10B12/31 ,  H10B12/482 ,  H01L21/3213

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US20210210432A1

公开(公告)日：2021-07-08

申请号：US17205462

申请日：2021-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L27/108 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

公开(公告)号：US10373960B2

公开(公告)日：2019-08-06

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/28 ,  H01L21/71 ,  H01L27/108 ,  H01L29/792 ,  H01L21/8234

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US20190206875A1

公开(公告)日：2019-07-04

申请号：US16295562

申请日：2019-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Taejin Park ,  Yoosang Hwang

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.

公开(公告)号：US09960170B1

公开(公告)日：2018-05-01

申请号：US15614077

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Kiseok Lee ,  Keunnam Kim ,  Bong-Soo Kim ,  Jemin Park ,  Chan-Sic Yoon ,  Yoosang Hwang

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894

Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.

公开(公告)号：US20180019244A1

公开(公告)日：2018-01-18

申请号：US15646380

申请日：2017-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/762 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L27/10814 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/32051 ,  H01L21/32134 ,  H01L21/76224 ,  H01L23/5283 ,  H01L23/53257 ,  H01L23/53261 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/0649

Abstract: A semiconductor device includes a substrate, a bit line structure on the substrate, a first contact structure on a sidewall of the bit line structure, a second contact structure on the bit line structure and spaced apart from the first contact structure across the bit line structure, and an insulation pattern between the bit line structure and the first contact structure. The second contact structure covers at least a portion of a top surface of the bit line structure. The insulation pattern comprises a protrusion that protrudes from a sidewall of the insulation pattern that immediately adjacent to the bit line structure. The protrusion protrudes in a first direction parallel to a top surface of the substrate.