公开(公告)号：US20250056794A1

公开(公告)日：2025-02-13

申请号：US18653191

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyun Lim ,  Soobin Kim ,  Seungyoung Seo ,  Sunwoo Heo

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral circuit region, a peripheral circuit gate line on the peripheral circuit region of the substrate, an interlayer insulating layer surrounding the peripheral circuit gate line, a contact plug passing through the interlayer insulating layer to be connected to the substrate, a wiring pad on the contact plug, and a metal via being in contact with the wiring pad, wherein a first sidewall and a second sidewall of the contact plug form acute angles with an upper surface of the contact plug, and a first sidewall and a second sidewall of the wiring pad form acute angles with a lower surface of the wiring pad.

公开(公告)号：US20220077152A1

公开(公告)日：2022-03-10

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US20250105150A1

公开(公告)日：2025-03-27

申请号：US18625407

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeon Il Lee ,  Seryeun Yang ,  Dongkyun Lim

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device may include a substrate that includes a first surface and a second surface opposite to each other, a first driving transistor and a second driving transistor on the first surface of the substrate, a first insulation layer on the first surface of the substrate, a second insulation layer on the second surface of the substrate, a first penetration electrode and a second penetration electrode that extend into the substrate, the first insulation layer, and the second insulation layer, a first contact plug extending in the first insulation layer and electrically connected to the first driving transistor and the first penetration electrode, and a second contact plug extending in the substrate and the second insulation layer and electrically connected to the second driving transistor and the second penetration electrode.

公开(公告)号：US20240306376A1

公开(公告)日：2024-09-12

申请号：US18391828

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Sunwoo Heo ,  Soobin Kim ,  Jinsub Kim ,  Seungyoung Seo ,  Taeyong Song

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including an active region; a cell gate structure disposed in the substrate, crossing the active region, and extending in a first horizontal direction; bitline structures crossing the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction; a contact plug disposed between the bitline structures; a landing pad structure disposed on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, wherein the upper landing pad includes a cavity; a conductive pattern disposed in the cavity of the upper landing pad; and an insulating pattern structure in contact with one of the bitline structures and in contact with the landing pad structure.

公开(公告)号：US20250149508A1

公开(公告)日：2025-05-08

申请号：US18674207

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Seryeun Yang ,  Dongkyun Lim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device includes a first chip structure that includes a memory structure and a cell routing interconnection structure that is electrically connected to the memory structure, a second chip structure that is on the first chip structure and includes a first peripheral circuit, a second peripheral circuit, a first peripheral routing interconnection structure that is electrically connected to the first peripheral circuit and the cell routing interconnection structure, and a second peripheral routing interconnection structure that is electrically connected to the second peripheral circuit, and a connection structure that extends into the first chip structure and the second chip structure, where the connection structure includes: a first connection pad, a second connection pad that overlaps the first connection pad, and an intermediate connection structure that is between the first connection pad and the second connection pad and is electrically connected to the second peripheral routing interconnection structure.

公开(公告)号：US11690213B2

公开(公告)日：2023-06-27

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H10B12/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B12/315 ,  H01L29/4941 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.