公开(公告)号：US20250056794A1

公开(公告)日：2025-02-13

申请号：US18653191

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyun Lim ,  Soobin Kim ,  Seungyoung Seo ,  Sunwoo Heo

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral circuit region, a peripheral circuit gate line on the peripheral circuit region of the substrate, an interlayer insulating layer surrounding the peripheral circuit gate line, a contact plug passing through the interlayer insulating layer to be connected to the substrate, a wiring pad on the contact plug, and a metal via being in contact with the wiring pad, wherein a first sidewall and a second sidewall of the contact plug form acute angles with an upper surface of the contact plug, and a first sidewall and a second sidewall of the wiring pad form acute angles with a lower surface of the wiring pad.

公开(公告)号：US20240306376A1

公开(公告)日：2024-09-12

申请号：US18391828

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Sunwoo Heo ,  Soobin Kim ,  Jinsub Kim ,  Seungyoung Seo ,  Taeyong Song

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including an active region; a cell gate structure disposed in the substrate, crossing the active region, and extending in a first horizontal direction; bitline structures crossing the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction; a contact plug disposed between the bitline structures; a landing pad structure disposed on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, wherein the upper landing pad includes a cavity; a conductive pattern disposed in the cavity of the upper landing pad; and an insulating pattern structure in contact with one of the bitline structures and in contact with the landing pad structure.

公开(公告)号：US11574915B2

公开(公告)日：2023-02-07

申请号：US17328228

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wooyoung Choi ,  Woonghwi Bae ,  Jinwoo Bae ,  Chaelin Yoon ,  Sunghee Han ,  Sunwoo Heo ,  Deoksung Hwang

IPC: H01L27/108

Abstract: A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.