公开(公告)号：US20220077152A1

公开(公告)日：2022-03-10

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US11690213B2

公开(公告)日：2023-06-27

申请号：US17199740

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Lim ,  Youngsin Kim ,  Kijin Park ,  Hoju Song ,  Dongkwan Yang ,  Sangho Yun ,  Gyuhyun Lee ,  Jieun Lee ,  Seunguk Han ,  Yoongi Hong

IPC: H10B12/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC classification number: H10B12/315 ,  H01L29/4941 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/7833

Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

公开(公告)号：US20230005926A1

公开(公告)日：2023-01-05

申请号：US17839344

申请日：2022-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkwan Yang ,  Jaybok Choi ,  Yongseok Ahn

IPC: H01L27/108

Abstract: An integrated circuit device includes: a plurality of bit lines extending on a substrate in a first direction parallel to an upper surface of the substrate; a plurality of insulation capping structures respectively arranged on the plurality of bit lines, extending in the first direction, and including a first insulating material; a conductive plug between two adjacent bit lines among the plurality of bit lines on the substrate; a top capping layer arranged on the plurality of insulation capping structures and including a second insulating material different from the first insulating material; and a landing pad arranged on the conductive plug and arranged on a sidewall of a corresponding insulation capping structure among the plurality of insulation capping structures and the top capping layer.