公开(公告)号：US10211091B2

公开(公告)日：2019-02-19

申请号：US15334469

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/108

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US12130242B2

公开(公告)日：2024-10-29

申请号：US18446837

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doyoung Yoon ,  Jeongho Ahn ,  Dongryul Lee ,  Dongchul Ihm ,  Chungsam Jun

IPC: G01N21/95 ,  G01N21/88 ,  G01N21/956 ,  H01L21/66

CPC classification number: G01N21/9501 ,  G01N21/8806 ,  G01N21/956 ,  H01L22/12

Abstract: A semiconductor wafer inspection system includes a wafer chuck disposed inside a chamber and on which a wafer is disposed, a light source configured to emit light for inspecting a pattern on the wafer to the wafer, an inspection controller configured to control the driving of the light source, a cooling gas gun disposed adjacent to the light source and configured to spray a cooling gas on a surface of the wafer, and a cooling controller configured to supply cooling air to the wafer chuck before light is emitted to the wafer and supply the cooling gas to the cooling gas gun.

公开(公告)号：US11754510B2

公开(公告)日：2023-09-12

申请号：US17501318

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doyoung Yoon ,  Jeongho Ahn ,  Dongryul Lee ,  Dongchul Ihm ,  Chungsam Jun

IPC: G01N21/95 ,  H01L21/66 ,  G01N21/88 ,  G01N21/956

CPC classification number: G01N21/9501 ,  G01N21/8806 ,  G01N21/956 ,  H01L22/12

Abstract: A semiconductor wafer inspection system includes a wafer chuck disposed inside a chamber and on which a wafer is disposed, a light source configured to emit light for inspecting a pattern on the wafer to the wafer, an inspection controller configured to control the driving of the light source, a cooling gas gun disposed adjacent to the light source and configured to spray a cooling gas on a surface of the wafer, and a cooling controller configured to supply cooling air to the wafer chuck before light is emitted to the wafer and supply the cooling gas to the cooling gas gun.

公开(公告)号：US10796950B2

公开(公告)日：2020-10-06

申请号：US16238172

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US11646225B2

公开(公告)日：2023-05-09

申请号：US17039431

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

IPC: H01L27/10 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.