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    COOKING APPLIANCE AND METHOD FOR CONTROLLING THE SAME
    1.
    发明申请
    COOKING APPLIANCE AND METHOD FOR CONTROLLING THE SAME 有权

    公开(公告)号：US20250137653A1

    公开(公告)日：2025-05-01

    申请号：US18818093

    申请日：2024-08-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehyuk Lee ,  Eunha Choi ,  Jihye Kwon ,  Joayoung Lee

    IPC: F24C7/08 ,  H05B6/68

    Abstract: A cooking appliance providing context of cooking food as an image and a method for controlling the same are provided. The cooking appliance may be configured to determine an internal temperature of a cooking thing based on at least one surface temperature sensed on a surface of the cooking thing by a non-contact temperature sensor, obtain a reference cross-sectional image corresponding to the determined internal temperature among reference cross-sectional images pre-registered for each cooking progress state of the cooking thing, as a virtual cross-sectional image for feeding back the cooking progress state, and output the same.

    SEMICONDUCTOR DEVICE WITH CMOS INVERTER
    2.
    发明公开
    SEMICONDUCTOR DEVICE WITH CMOS INVERTER 审中-公开

    公开(公告)号：US20230178550A1

    公开(公告)日：2023-06-08

    申请号：US17937473

    申请日：2022-10-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Beomyong Hwang ,  Jihye Kwon ,  Jiyoung Kim

    IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L29/41741 ,  H01L29/7827 ,  H01L21/823871 ,  H01L21/823885

    Abstract: A semiconductor device includes a buried insulation layer pattern on a lower substrate. A first semiconductor pattern and a second semiconductor pattern pattern are disposed on on the buried insulation layer pattern. A lower conductive pattern is formed in a lower portion of a first recess between the first and second semiconductor patterns, and the lower conductive pattern may contact lower sidewalls of the first and second semiconductor patterns. A common gate structure formed on the lower conductive pattern fills a remaining portion of the first recess. The first semiconductor pattern may include a first impurity region, a first channel region, and a second impurity region sequentially stacked from an upper surface of the first semiconductor towards the lower substrate. The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.

    SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS
    3.
    发明公开
    SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS 审中-公开

    公开(公告)号：US20240260250A1

    公开(公告)日：2024-08-01

    申请号：US18506405

    申请日：2023-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinseong Lee ,  Jihye Kwon ,  Jihun Kim ,  Kyosuk Chae

    IPC: H10B12/00

    CPC classification number: H10B12/0335 ,  H10B12/482 ,  H10B12/315

    Abstract: A semiconductor device includes a substrate including an active region. A gate structure is disposed in the substrate and extends to traverse the active region in a first horizontal direction. Bit line structures traverse the gate structure and extend in a second horizontal direction, intersecting the first horizontal direction. Fence structures are disposed between the bit line structures. The fence structures are spaced apart from each other in the second horizontal direction. A contact plug is disposed between the bit line structures and between the fence structures. The contact plug includes first and second side surfaces that are spaced apart from each other in the second horizontal direction and third and fourth side surfaces that are spaced apart from each other in the first horizontal direction. A doping concentration of the first side surface is higher than a doping concentration of the third side surface.

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