公开(公告)号：US20240331774A1

公开(公告)日：2024-10-03

申请号：US18367677

申请日：2023-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gangmin Lee ,  Jaehue Shin ,  Daeseok Byeon ,  Yongsung Cho

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C29/10

CPC classification number: G11C16/0491 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C29/10

Abstract: A nonvolatile memory device may include a page buffer, a control signal generator, and a current mirror. The page buffer may be connected to a bitline and may allow a replicated current to flow through a ground terminal in response to a first control signal and a second control signal. The control signal generator may output the first control signal and the second control signal to the page buffer. The current mirror may output, in a virtual cell mode, a control voltage corresponding to a bias current. The control voltage may correspond to the first control signal.

公开(公告)号：US20240055055A1

公开(公告)日：2024-02-15

申请号：US18197258

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsung Cho ,  Inho Kang ,  Insu Kim ,  Jaehue Shin

IPC: G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  H01L25/0657 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units. Each of the plurality of page buffer units includes a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.

公开(公告)号：US20240363172A1

公开(公告)日：2024-10-31

申请号：US18509021

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjeong Heo ,  Jaehue Shin ,  Daeseok Byeon ,  Yongsung Cho

IPC: G11C16/24 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483

Abstract: A nonvolatile memory device includes a plurality of tri-state latches, a sensing node circuit configured to electrically couple a sensing node therein to a bitline of the memory device, a transfer node circuit configured to electrically couple a transfer node therein to the plurality of tri-state latches, and a node connection circuit configured to electrically connect the transfer node to the sensing node. In addition, the transfer node circuit and the node connection circuit are collectively configured to simultaneously reflect data stored in at least two of the plurality of tri-state latches to the sensing node, in response to a dump sequence operation.