公开(公告)号：US11342234B2

公开(公告)日：2022-05-24

申请号：US16846724

申请日：2020-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Chanho Kim

IPC: G01R31/26 ,  H01L23/552 ,  H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L21/66 ,  H01L23/544 ,  G01N21/95

Abstract: A semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an outer crack detection structure, a plurality of inner crack detection structures and a plurality of path selection circuits. The semiconductor die includes a central region and an edge region surrounding the central region. The semiconductor integrated circuit is in a plurality of sub regions of the central region. The outer crack detection structure is in the edge region. The plurality of inner crack detection structures are respectively in the plurality of sub regions, respectively. The path selection circuits are configured to control an electrical connection between the outer crack detection structure and the plurality of inner crack detection structures. A crack in the central region in addition to a crack in the edge region may be detected efficiently through selective electrical connection of the outer crack detection structure and the inner crack detection structures.

公开(公告)号：US11237955B2

公开(公告)日：2022-02-01

申请号：US17007501

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G11C16/34 ,  G06F12/02 ,  G06F12/123 ,  G06F12/0811 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4074 ,  G06F12/14

Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US11227815B2

公开(公告)日：2022-01-18

申请号：US16827746

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyo Kim ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor die includes first pads, switches that are electrically connected with the first pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the first pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the first pads based on a result of the operations, and a switch controller that controls the switches so that the first pads communicate with the test signal generator during a test operation and that the first pads communicate with the internal circuits after a completion of the test operation.

公开(公告)号：US11189634B2

公开(公告)日：2021-11-30

申请号：US16705395

申请日：2019-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11573 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11565 ,  H01L23/532

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US20210091105A1

公开(公告)日：2021-03-25

申请号：US16923636

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/768

Abstract: An integrated circuit (IC) device includes a peripheral circuit structure, a memory stack including a plurality of gate lines overlapping the peripheral circuit structure in a vertical direction on the peripheral circuit structure, an upper substrate between the peripheral circuit structure and the memory stack, the upper substrate including a through hole positioned below a memory cell region of the memory stack, a word line cut region extending lengthwise in a first lateral direction across the memory stack and the through hole, and a common source line located in the word line cut region, the common source line including a first portion extending lengthwise in the first lateral direction on the upper substrate and a second portion integrally connected to the first portion, the second portion penetrating the upper substrate through the through hole from an upper portion of the upper substrate and extending into the peripheral circuit structure.

公开(公告)号：US10797066B2

公开(公告)日：2020-10-06

申请号：US16030170

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Yeol Lee ,  Chanho Kim

IPC: H01L27/11575 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/04

Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.

公开(公告)号：US12211830B2

公开(公告)日：2025-01-28

申请号：US18179056

申请日：2023-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L25/18 ,  H01L29/40

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

公开(公告)号：US20230317655A1

公开(公告)日：2023-10-05

申请号：US18328359

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong PARK ,  Chanho Kim ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L22/20 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US11721655B2

公开(公告)日：2023-08-08

申请号：US17381782

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Chanho Kim ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/66 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L22/20 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US11513730B2

公开(公告)日：2022-11-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F11/00 ,  G06F3/06 ,  G05D1/00 ,  G06F13/16 ,  G11C5/02 ,  B60W50/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.