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公开(公告)号：US12107061B2
公开(公告)日：2024-10-01
申请号：US17513132
申请日：2021-10-28
发明人： Homoon Shin , Jooyong Park , Hongsoo Jeon , Pansuk Kwak
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC分类号： H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.
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公开(公告)号：US20240065004A1
公开(公告)日：2024-02-22
申请号：US18366723
申请日：2023-08-08
发明人： Jooyong Park , Seungyeon Kim , Daeseok Byeon
CPC分类号： H10B80/00 , H10B43/27 , H10B43/35 , H01L25/0657 , H01L25/18 , H01L24/08 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.
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公开(公告)号：US11901033B2
公开(公告)日：2024-02-13
申请号：US18149302
申请日：2023-01-03
发明人： Jooyong Park , Minsu Kim , Daeseok Byeon , Pansuk Kwak
IPC分类号： G11C29/00 , G06F11/20 , G11C16/04 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/12 , G11C29/02 , G11C29/52 , G11C29/42 , G11C29/24
CPC分类号： G11C29/838 , G06F11/2094 , G11C16/0483 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/349 , G11C16/3472 , G11C29/02 , G11C29/24 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/70 , G11C29/702 , G11C29/785 , G11C29/789 , G11C2029/1204
摘要： A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
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公开(公告)号：US20230148408A1
公开(公告)日：2023-05-11
申请号：US17982550
申请日：2022-11-08
发明人： Jooyong Park , Wontaeck Jung , Nayeon Kim , Jiwon Seo , Seungyong Hyun
CPC分类号： G11C16/3459 , G11C16/3468 , G11C16/08
摘要： An operation method of a memory device for programming memory cells to a plurality of program states includes providing a series of program pulses to selected memory cells, performing a first verification operation of verifying a target program state among the plurality of program states, performing, when the first verification operation is passed, a second verification operation of detecting fail cells among the selected memory cells to determine if these memory cells have been overprogrammed. When the number of detected fail cells is greater than or equal to a reference value, the program operation may be terminated for that location and the data may be written to another location.
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公开(公告)号：US20230147765A1
公开(公告)日：2023-05-11
申请号：US17953715
申请日：2022-09-27
发明人： Seungyeon Kim , Jooyong Park , Hongsoo Jeon
IPC分类号： G11C11/4099 , G11C11/4097 , G11C11/408
CPC分类号： G11C11/4099 , G11C11/4097 , G11C11/4085 , G11C11/4087
摘要： A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
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公开(公告)号：US11574700B2
公开(公告)日：2023-02-07
申请号：US17245568
申请日：2021-04-30
发明人： Jooyong Park , Minsu Kim , Daeseok Byeon , Pansuk Kwak
IPC分类号： G11C29/00 , G06F11/20 , G11C16/04 , G11C29/44 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/12 , G11C29/02 , G11C29/52 , G11C29/42 , G11C29/24
摘要： A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.
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公开(公告)号：US11120843B2
公开(公告)日：2021-09-14
申请号：US16816476
申请日：2020-03-12
发明人： Jooyong Park , Chanho Kim , Daeseok Byeon
IPC分类号： H01L23/522 , G11C5/06 , G11C5/04 , G11C7/18
摘要： A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.
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公开(公告)号：US10832782B2
公开(公告)日：2020-11-10
申请号：US16562999
申请日：2019-09-06
发明人： Jooyong Park
摘要： A nonvolatile memory device that performs a read operation during which row decoder circuitry applies a turn on voltage to a first ground selection line selected from a plurality of ground selection lines, applies a turn off voltage to at least one second ground selection line selected from the plurality of ground selection lines, the at least one second ground selection line being selected from the plurality of ground selection lines based on a read address associated with the read operation, and applies the turn off voltage to an unselected ground selection line among the plurality of ground selection lines after applying a prepulse voltage to the unselected ground selection line.
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公开(公告)号：US10685713B2
公开(公告)日：2020-06-16
申请号：US16163968
申请日：2018-10-18
发明人： Jooyong Park , Jin-Young Kim , Kuihan Ko , Han Il Park , Bongsoon Lim
摘要： A storage device includes a nonvolatile memory device that includes memory blocks, each including memory cells, and a controller that receives a first write request from an external host device. Depending on the first write request, the controller transmits a first sanitize command to the nonvolatile memory device and transmits first write data and a first write command associated with the first write request to the nonvolatile memory device. The nonvolatile memory device is configured to sanitize first data previously written to first memory cells of a first memory block of the memory blocks in response to the first sanitize command. The nonvolatile memory device is further configured to write the first write data to second memory cells of the first memory block in response to the first write command.
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公开(公告)号：US20240049481A1
公开(公告)日：2024-02-08
申请号：US18188311
申请日：2023-03-22
发明人： Seungyeon Kim , Takuya Futatsuyama , Jooyong Park , Beakhyung Cho
IPC分类号： H10B80/00
CPC分类号： H10B80/00
摘要： A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes memory cells electrically connected to bit lines each extending in a first direction and word lines each extending in a second direction and stacked in a vertical direction, word line pads which respectively correspond to the word lines and are arranged in a stair shape, and word line contacts respectively electrically connected to the word line pads. The second semiconductor layer includes pass transistors respectively electrically connected to the word line contacts to respectively overlap the word line pads in the vertical direction. Each of the word line pads has a first width in the first direction and a second width in the second direction. Each of the pass transistors has a first pitch in the first direction and a second pitch in the second direction.
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