公开(公告)号：US11887672B2

公开(公告)日：2024-01-30

申请号：US17693013

申请日：2022-03-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Myeong-Woo Lee ,  Seungyeon Kim ,  Dongha Shin ,  Beakhyung Cho

IPC分类号： G11C16/16 ,  G11C16/24 ,  G11C16/30 ,  G11C16/28 ,  G11C7/10

CPC分类号： G11C16/16 ,  G11C7/1039 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

摘要： A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

公开(公告)号：US20240049481A1

公开(公告)日：2024-02-08

申请号：US18188311

申请日：2023-03-22

申请人： Samsung Electronics Co., Ltd.

发明人： Seungyeon Kim ,  Takuya Futatsuyama ,  Jooyong Park ,  Beakhyung Cho

IPC分类号： H10B80/00

CPC分类号： H10B80/00

摘要： A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes memory cells electrically connected to bit lines each extending in a first direction and word lines each extending in a second direction and stacked in a vertical direction, word line pads which respectively correspond to the word lines and are arranged in a stair shape, and word line contacts respectively electrically connected to the word line pads. The second semiconductor layer includes pass transistors respectively electrically connected to the word line contacts to respectively overlap the word line pads in the vertical direction. Each of the word line pads has a first width in the first direction and a second width in the second direction. Each of the pass transistors has a first pitch in the first direction and a second pitch in the second direction.

公开(公告)号：US20240105267A1

公开(公告)日：2024-03-28

申请号：US18201331

申请日：2023-05-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Inho Kang ,  Daeseok Byeon ,  Beakhyung Cho ,  Min-Hwi Kim ,  Yongsung Cho ,  Gyosoo Choo

IPC分类号： G11C16/24 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00

CPC分类号： G11C16/24 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

摘要： Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.