公开(公告)号：US20230054754A1

公开(公告)日：2023-02-23

申请号：US17702291

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

IPC: G06F11/10 ,  G06F11/07 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074

Abstract: A storage device includes a NAND flash memory device, an auxiliary memory device and a storage controller to control the NAND flash memory device and the auxiliary memory device. The storage controller includes a processor, an error correction code (ECC) engine and a memory interface. The processor executes a flash translation layer (FTL) loaded onto an on-chip memory. The ECC engine generates first parity bits for user data to be stored in a target page of the NAND flash memory device based on error attribute of a target memory region associated with the target page, and selectively generates additional parity bits for the user data under control of the processor. The memory interface transmits the user data and the first parity bits to the NAND flash memory device, and selectively transmits the additional parity bits to the auxiliary memory device.

公开(公告)号：US10777282B2

公开(公告)日：2020-09-15

申请号：US16531787

申请日：2019-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Young-geun Lee

IPC: G11C16/34 ,  G11C16/26 ,  G11C29/42 ,  G06F11/22 ,  G06F13/16 ,  G11C29/04

Abstract: A memory controller to control a memory device includes an Error Checking and Correcting (ECC) engine to perform error detection on data read from the memory device and a data operation manager. The data operation manager is to control a first rewrite operation of the memory device on selected memory cells to compensate for a drift in a distribution of the selected memory cells, based on a result of a test read operation of the memory device on test cells, determine a distribution adjustment degree based on a result of a normal read operation, as an ECC decoding operation corresponding to the normal read operation of the memory device is successfully performed by using the ECC engine, and control a second rewrite operation of the memory device based on the determined distribution adjustment degree.

公开(公告)号：US12125534B2

公开(公告)日：2024-10-22

申请号：US17935122

申请日：2022-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggul Song ,  Junyeong Seok ,  Eun Chu Oh ,  Byungchul Jang

IPC: G11C8/00 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B69/00

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H10B69/00

Abstract: A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

公开(公告)号：US20230154537A1

公开(公告)日：2023-05-18

申请号：US17935122

申请日：2022-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGGUL SONG ,  Junyeong Seok ,  Eun Chu Oh ,  Byungchul Jang

IPC: G11C16/04 ,  G11C16/08 ,  H01L27/115 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H01L27/115

Abstract: A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

公开(公告)号：US20230111033A1

公开(公告)日：2023-04-13

申请号：US17749691

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

Abstract: A storage device, including a nonvolatile memory device and a storage controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array including a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes, and a word-line cut region dividing the plurality of word-lines into a plurality of memory blocks. The storage controller groups a plurality of target memory cells into outer cells and inner cells. The storage controller includes an error correction code (ECC) decoder configured to perform an ECC decoding operation by obtaining outer cell bits and inner cell bits during a read operation on the plurality of target memory cells, and applying different log likelihood ratio (LLR) values to the outer cell bits and the inner cell bits.

公开(公告)号：US10916314B2

公开(公告)日：2021-02-09

申请号：US16744763

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Jin Shin ,  Ji Su Kim ,  Dae Seok Byeon ,  Ji Sang Lee ,  Jun Jin Kong ,  Eun Chu Oh

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

公开(公告)号：US09691477B2

公开(公告)日：2017-06-27

申请号：US15042516

申请日：2016-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Jun Jin Kong ,  Young Bae Kim ,  Hong Rak Son ,  Pil Sang Yoon ,  Han Shin Shin

IPC: G11C13/00 ,  G11C7/10 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C7/1006 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0076

Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

公开(公告)号：US12288590B2

公开(公告)日：2025-04-29

申请号：US17750581

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Wijik Lee ,  Byungchul Jang

IPC: G11C29/42 ,  G11C7/10 ,  G11C29/44 ,  G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C29/12 ,  G11C29/52 ,  H03M13/05 ,  H03M13/29

Abstract: A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

公开(公告)号：US20240184458A1

公开(公告)日：2024-06-06

申请号：US18235678

申请日：2023-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Beomkyu Shin

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679

Abstract: A storage device includes at least one non-volatile memory including a plurality of blocks, each block of the plurality of blocks including a plurality of independently erasable sub-blocks. The storage device further includes a storage controller configured to select an erase mode from among a plurality of erase modes according to at least one of an operation schedule and a power consumption of the non-volatile memory, and control an erase operation of the non-volatile memory, according to the selected erase mode. Based on the selected erase mode being a first sub-block erase mode, the storage controller controls an erase operation with respect to one selected sub-block of a selected block. Based on the selected erase mode being a second sub-block erase mode, the storage controller controls an erase operation with respect to two or more selected sub-blocks of the selected block.

公开(公告)号：US20230112694A1

公开(公告)日：2023-04-13

申请号：US17750581

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Wijik Lee ,  Byungchul Jang

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10

Abstract: A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.