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1.发明申请公开(公告)号：US20210334225A1
公开(公告)日：2021-10-28
申请号：US17241564
申请日：2021-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungho Seo , Kwanwoo Noh , Myungsub Shin , Dongwoo Nam
Abstract: A storage device capable of performing high-speed link startup and a storage system including the storage device are disclosed. A link startup method of the storage device includes receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device, comparing a length of the received line-reset signal with a first reference time, and performing a link startup operation in a high-speed mode or a low-speed mode between the storage device and the host according to a comparing result.
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公开(公告)号：US11934691B2
公开(公告)日：2024-03-19
申请号：US18304782
申请日：2023-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongwoo Nam , Sungho Seo , Kwanwoo Noh , Myungsub Shin , Haesung Jung
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F13/1668 , G06F13/385 , G06F13/4278
Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.
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公开(公告)号：US20230259303A1
公开(公告)日：2023-08-17
申请号：US18304782
申请日：2023-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongwoo NAM , Sungho Seo , Kwanwoo Noh , Myungsub Shin , Haesung Jung
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F13/1668 , G06F13/385 , G06F13/4278
Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.
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公开(公告)号：US10437498B2
公开(公告)日：2019-10-08
申请号：US15697900
申请日：2017-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Hyuntae Park , Sungho Seo , Hwaseok Oh , Youngmin Lee , JinHyeok Choi
Abstract: An electronic device includes an application processor; and a first storage device that is, connected to the application processor and directly communicates with the application processor, and connected to a second storage device such that the second storage device communicates with the application processor through the first storage device, wherein the first storage device includes a reset converter configured to generate a software reset signal in response to a hardware reset signal received from the application processor, and wherein the software reset signal resets the second storage device.
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公开(公告)号：US12067287B2
公开(公告)日：2024-08-20
申请号：US17685024
申请日：2022-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kwanwoo Noh , Hyeonjong Song , Wijik Lee , Hongrak Son , Dongmin Shin , Seonghyeog Choi
CPC classification number: G06F3/0658 , G06F3/0614 , G06F3/0679 , G11C16/0483
Abstract: Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.
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Patent Agency Ranking
公开(公告)号：US11961553B2
公开(公告)日：2024-04-16
申请号：US17804851
申请日：2022-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wijik Lee , Kwanwoo Noh , Hyeonjong Song
IPC: G11C7/00 , G11C11/4074 , G11C11/4078 , G11C11/4096
CPC classification number: G11C11/4096 , G11C11/4074 , G11C11/4078
Abstract: A nonvolatile memory device includes a plurality of memory cells that have a first state and a second state different from each other. A method of searching a read voltage of the nonvolatile memory device includes determining a number n that represents a number of times a data read operation is performed, selecting n read voltage levels of the read voltage such that a number of read voltage levels is equal to the number of times the data read operation, where the n read voltage levels differ from each other, generating n cell count values by performing n data read operations on the plurality of memory cells using all of the n read voltage levels, and generating an optimal read voltage level of the read voltage by performing a regression analysis based on a first-order polynomial using the n read voltage levels and the n cell count values.
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7.发明授权公开(公告)号：US11625342B2
公开(公告)日：2023-04-11
申请号：US17241564
申请日：2021-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungho Seo , Kwanwoo Noh , Myungsub Shin , Dongwoo Nam
Abstract: A storage device capable of performing high-speed link startup and a storage system including the storage device are disclosed. A link startup method of the storage device includes receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device, comparing a length of the received line-reset signal with a first reference time, and performing a link startup operation in a high-speed mode or a low-speed mode between the storage device and the host according to a comparing result.
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公开(公告)号：US20250014647A1
公开(公告)日：2025-01-09
申请号：US18408126
申请日：2024-01-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minuk KIM , Soonyoung Kang , Kwanwoo Noh , Dong-Min Shin
Abstract: A storage device includes a nonvolatile memory device including a plurality of first memory cells coupled to a first wordline and a plurality of second memory cells coupled to a second wordline, the first wordline and the second wordline being adjacent to each other, and a storage controller configured to control the nonvolatile memory device. The storage controller is further configured to encode data to be programmed into the plurality of second memory cells, based on a program state of each of the plurality of first memory cells, and encode the data to be programmed into the second wordline such that a first portion of the data to be written into a first portion of the plurality of second memory cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second memory cells satisfies a second condition.
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公开(公告)号：US11726677B2
公开(公告)日：2023-08-15
申请号：US17142627
申请日：2021-01-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kwanwoo Noh , Sungho Seo , Yongwoo Jeong
IPC: G06F3/06 , G06F9/44 , G06F9/4401 , G06F1/04
CPC classification number: G06F3/0625 , G06F1/04 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F9/4418
Abstract: Disclosed is a storage device which includes an interface circuit that exchanges data with a host device, and a power management unit that supplies a power to the interface circuit. The interface circuit includes a first input terminal receiving a first signal from the host device, a second input terminal receiving a second signal complementary to the first signal from the host device, a receive module processing the first signal and the second signal, a squelch circuit detecting levels of the first signal and the second signal, and a reference clock detector detecting whether a reference clock for operating the storage device is received. The power management unit selectively supplies a power to the squelch circuit based on a result of the detection by the reference clock detector.
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公开(公告)号：US11675531B2
公开(公告)日：2023-06-13
申请号：US17328225
申请日：2021-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongwoo Nam , Sungho Seo , Kwanwoo Noh , Myungsub Shin , Haesung Jung
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F13/1668 , G06F13/385 , G06F13/4278
Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.
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