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公开(公告)号：US12235672B2
公开(公告)日：2025-02-25
申请号：US18363906
申请日：2023-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung Maeng , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
IPC: G06F1/10
Abstract: An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.
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公开(公告)号：US11953001B2
公开(公告)日：2024-04-09
申请号：US17747991
申请日：2022-05-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Soodol Park , Joonhyung Kim , Munseong Kwon , Jaewoo Park , Hyolim Heo
CPC classification number: F04C15/0088 , F04C2/12 , F04C29/02 , F04C29/026 , F04C2240/30
Abstract: A horizontal type rotary compressor includes a case including an inlet and an outlet and configured to store oil, a compressor having a compression space in which refrigerant is accommodated, a driver to drive the compressor, a rotating shaft to connect the driver and the compressor, an oil feed pipe disposed at a side of the compressor, a first plate configured to divide the case into a first area for the driver and a second area for the compressor. The first plate including a discharge hole through which compressed refrigerant is discharged from the compressor to the first area. A second plate dividing the case into the second area and a third area in which the oil feed pipe communicates with the outlet, and includes a second hole formed at the upper side to communicate the second and third areas. The first and second plates forming an oil flow path.
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公开(公告)号：US11940830B2
公开(公告)日：2024-03-26
申请号：US17709853
申请日：2022-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinook Jung , Jaewoo Park , Junhan Choi , Myoungbo Kwak , Junghwan Choi
IPC: G11C11/4074 , G05F1/575 , G11C11/4076 , G11C11/4093
CPC classification number: G05F1/575 , G11C11/4074 , G11C11/4076 , G11C11/4093
Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.
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公开(公告)号：US11888486B2
公开(公告)日：2024-01-30
申请号：US17872527
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinook Jung , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
CPC classification number: H03K5/01 , H03H11/16 , H03K2005/00019
Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.
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公开(公告)号：US11797038B2
公开(公告)日：2023-10-24
申请号：US17577201
申请日：2022-01-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woochul Jung , Myoungbo Kwak , Jaewoo Park , Eunseok Shin , Junhan Choi
Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.
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Patent Agency Ranking
公开(公告)号：US20230253018A1
公开(公告)日：2023-08-10
申请号：US18134618
申请日：2023-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junyoung Park , Jaewoo Park , Younghoon Son , Youngdon Choi , Junghwan Choi
CPC classification number: G11C5/147 , G11C7/1063 , G11C7/1069 , G11C7/109 , G11C7/1096 , G11C11/565 , H04L25/028 , H04L25/4917 , G11C2207/101
Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.
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公开(公告)号：US11627021B2
公开(公告)日：2023-04-11
申请号：US17563406
申请日：2021-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaewoo Park , Youngdon Choi , Junghwan Choi , Changsik Yoo
Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.
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公开(公告)号：US20230099738A1
公开(公告)日：2023-03-30
申请号：US17872527
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinook Jung , Jaewoo Park , Myoungbo Kwak , Junghwan Choi
Abstract: A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.
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公开(公告)号：US11594267B2
公开(公告)日：2023-02-28
申请号：US17230403
申请日：2021-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mingyu Lee , Jaewoo Park , Younghoon Son , Youngdon Choi , Hyungmin Jin , Junghwan Choi
Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.
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公开(公告)号：US20250038754A1
公开(公告)日：2025-01-30
申请号：US18658820
申请日：2024-05-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeha Kim , Young Choi , Myoungbo Kwak , Jaewoo Park , Youngdon Choi , Junghwan Choi
IPC: H03M1/06
Abstract: The present disclosure relates to successive approximation register analog-to-digital converters. An example successive approximation register analog-to-digital converter includes a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage, and a first analog-to-digital converter. The first analog-to-digital converter performs a feed forward equalization function by receiving the first input voltage and the second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.
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