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公开(公告)号：US11764800B2
公开(公告)日：2023-09-19
申请号：US17917185
申请日：2020-04-09
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
IPC: H03M1/12 , H03K17/296 , H03K17/62 , G11C27/02
CPC classification number: H03M1/1255 , H03K17/296 , G11C27/02 , H03K17/6285 , H03M1/124
Abstract: A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.
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公开(公告)号：US20230048012A1
公开(公告)日：2023-02-16
申请号：US17793628
申请日：2020-01-28
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
Abstract: A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.
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公开(公告)号：US12119962B2
公开(公告)日：2024-10-15
申请号：US17630375
申请日：2019-08-05
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
CPC classification number: H04L25/0272 , G01R27/32 , G01R31/2813 , G01R31/58 , G06F3/05 , H03M1/126
Abstract: A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.
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公开(公告)号：US20240030933A1
公开(公告)日：2024-01-25
申请号：US18041968
申请日：2020-09-15
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
IPC: H03M3/00
CPC classification number: H03M3/39
Abstract: A delta sigma modulator includes: an integrator that integrates differences between input signals and output signals of the delta sigma modulator; and a clocked comparator that outputs the output signals that are results of comparison between an output of the integrator and a threshold, at a timing synchronized with a clock signal. The integrator includes an operational amplifier, input resistors, feedback capacitors, and compensation inductors.
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公开(公告)号：US20220294671A1
公开(公告)日：2022-09-15
申请号：US17630375
申请日：2019-08-05
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
Abstract: A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.
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Patent Agency Ranking
公开(公告)号：US20240007120A1
公开(公告)日：2024-01-04
申请号：US18253530
申请日：2020-11-27
Applicant: Nippon Telegraph And Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/121
Abstract: A time interleaved ADC includes sub-ADCs that sample an analog input signal at a timing synchronized with a clock signal to convert the analog input signal into a digital output signal, delay circuits that apply a time difference to the analog input signal such that the analog input signal is input to each of the sub-ADCs with a delay of a first delay time in an arrangement order of the sub-ADCs, and delay circuits that apply a time difference to the clock signal such that the clock signal is input to each of the sub-ADCs with a delay of a second delay time in the arrangement order of the sub-ADCs.
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公开(公告)号：US11830560B2
公开(公告)日：2023-11-28
申请号：US17793628
申请日：2020-01-28
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
CPC classification number: G11C27/02 , H03K17/6285 , H03M1/124
Abstract: A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.
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公开(公告)号：US11824551B2
公开(公告)日：2023-11-21
申请号：US17916956
申请日：2020-04-07
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
Abstract: Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N−2k+1):(2k−1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).
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公开(公告)号：US20230155600A1
公开(公告)日：2023-05-18
申请号：US17916956
申请日：2020-04-07
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
Abstract: Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N-2k+1):(2k-1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).
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公开(公告)号：US20230141476A1
公开(公告)日：2023-05-11
申请号：US17917185
申请日：2020-04-09
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Naoki Terao , Munehiko Nagatani , Hideyuki Nosaka
IPC: H03M1/12 , H03K17/296
CPC classification number: H03M1/1255 , H03K17/296
Abstract: A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.
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