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公开(公告)号：US20240313746A1
公开(公告)日：2024-09-19
申请号：US18594207
申请日：2024-03-04
申请人： Qorvo US, Inc.
发明人： Masashi Nogawa
IPC分类号： H03K3/013 , H03K17/60 , H03K17/687
CPC分类号： H03K3/013 , H03K17/60 , H03K17/687
摘要： Embodiments of a power switching system are disclosed. In some embodiments, the system includes: a power transistor having a control terminal, a first transistor terminal, and a second transistor terminal; a current buffer that includes a bipolar junction transistor connected across the control terminal and the first transistor terminal, the bipolar junction transistor having a base; a gate driver circuit having a first circuit branch connected to the base of the bipolar junction transistor and a second circuit branch connected to the base of the bipolar junction transistor, wherein: the first circuit branch includes a first switch for opening and closing the first circuit branch; the second circuit branch includes a second switch for opening and closing the second circuit branch and a current source. In some embodiments, the power transistor is a Silicon Carbide field effect transistor or a Gallium Nitride field effect transistor.
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公开(公告)号：US12080784B2
公开(公告)日：2024-09-03
申请号：US18101712
申请日：2023-01-26
发明人： Tomoko Matsudai , Yoko Iwakaji , Takeshi Suwa
IPC分类号： H01L29/739 , H01L23/522 , H01L29/423 , H01L29/66 , H03K17/16 , H03K17/60
CPC分类号： H01L29/7397 , H01L23/5228 , H01L29/4236 , H01L29/66348 , H01L29/7393 , H01L29/7395 , H03K17/16 , H03K17/60
摘要： A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
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3.发明授权公开(公告)号：US12068893B2
公开(公告)日：2024-08-20
申请号：US18069664
申请日：2022-12-21
申请人： NXP USA, Inc.
发明人： Xueyang Geng , Xu Zhang , Xiaoqun Liu , Siamak Delshadpour
IPC分类号： H04L25/03 , H03F3/45 , H03K17/60 , H03K17/687
CPC分类号： H04L25/03878 , H03F3/45076 , H03K17/60 , H03K17/687 , H03F2203/45458 , H03F2203/45496
摘要： Embodiments of equalizers are disclosed. In an embodiment, an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.
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公开(公告)号：US20240213975A1
公开(公告)日：2024-06-27
申请号：US18438707
申请日：2024-02-12
摘要： An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.
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公开(公告)号：US20240175762A1
公开(公告)日：2024-05-30
申请号：US18432943
申请日：2024-02-05
发明人： Atul DWIVEDI , Pijush Kanti PANJA
CPC分类号： G01K7/00 , H03K17/60 , G01K2219/00
摘要： A method includes generating a voltage proportional to absolute temperature, generating an uncorrected voltage complementary to absolute temperature, and generating a correction voltage. The method further includes selectively sampling the voltage proportional to absolute temperature, the uncorrected voltage complementary to absolute temperature, and the correction voltage, providing those sampled voltages to inputs of an integrator, and then quantizing outputs of the integrator to produce a bitstream. The method continues with causing the integrator to integrate the voltage proportional to absolute temperature or causing the integrator to add the correction voltage to the uncorrected voltage complementary to absolute temperature to produce a corrected voltage complementary to absolute temperature and then integrate the corrected voltage complementary to absolute temperature, depending upon a most recent bit of the bitstream. The bitstream is filtered and decimated to produce a voltage indicative of a temperature of a chip on which the method is performed.
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公开(公告)号：US20240063783A1
公开(公告)日：2024-02-22
申请号：US17820424
申请日：2022-08-17
摘要： An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.
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公开(公告)号：US11901881B1
公开(公告)日：2024-02-13
申请号：US17820424
申请日：2022-08-17
摘要： An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.
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公开(公告)号：US11863199B2
公开(公告)日：2024-01-02
申请号：US17959887
申请日：2022-10-04
申请人： Socionext Inc.
发明人： Saul Darzy
摘要： Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.
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公开(公告)号：US11847004B2
公开(公告)日：2023-12-19
申请号：US17752593
申请日：2022-05-24
发明人： Hirofumi Otakeguchi
摘要： An electronic device includes a hold circuit and a microcomputer. The hold circuit is connected to a power control line from a control device. The microcomputer starts measuring the time of a second state when the power control line transitions from a first state to the second state due to the control device. The microcomputer controls a power supply circuit to turn on power when the second state continues for a first predetermined time, and operates the hold circuit to maintain the power control line in the second state for a second predetermined time after the first predetermined time has elapsed.
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公开(公告)号：US20230396932A1
公开(公告)日：2023-12-07
申请号：US18203974
申请日：2023-05-31
发明人： Stephan Leschka , Wolfgang Dreßler
CPC分类号： H04R19/016 , H03K17/60 , H04R3/007
摘要： An electret microphone is provided, comprising a microphone capsule with an output connection, a first input connection as an earth connection and a second input connection for providing a supply voltage for the microphone capsule and for leading out a microphone output signal of the microphone capsule, and a cascode consisting of a first and second transistor. An output connection of the microphone capsule is provided as input of the cascode. The second transistor is configured as a field effect transistor FET and the gate connection thereof is coupled to the output connection of the microphone capsule. A drain connection of the second transistor is coupled to an emitter connection of the first transistor as bipolar transistor or to a source connection of the first transistor as an FET transistor. Furthermore, a third transistor is provided as bipolar transistor, whose emitter connection is coupled to the second input connection. A collector connection of the third transistor is coupled via a capacitor to earth. A base connection of the third transistor is coupled via a resistance to the second input connection. The base connection of the third transistor is coupled to a collector connection of the first transistor as bipolar transistor or to a drain connection of the first transistor as FET transistor. A resistance is coupled between the drain connection of the second transistor and the collector connection of the third transistor.
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