公开(公告)号：US20240363521A1

公开(公告)日：2024-10-31

申请号：US18763697

申请日：2024-07-03

申请人： Socionext Inc.

发明人： Hideyuki KOMURO

IPC分类号： H01L23/50 ,  H01L27/02 ,  H01L27/088

CPC分类号： H01L23/50 ,  H01L27/0207 ,  H01L27/088

摘要： In a semiconductor integrated circuit device using buried power lines, a standard cell includes: a first buried power line extending in the X direction and supplying a first power supply voltage; a second buried power line extending in the X direction and supplying a second power supply voltage; and a first transistor connected to the first power line. The first buried power line is spaced from the first transistor in planar view and located closer to the center of the standard cell than the first transistor in the Y direction.

公开(公告)号：US20240355786A1

公开(公告)日：2024-10-24

申请号：US18762452

申请日：2024-07-02

申请人： SOCIONEXT INC.

发明人： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC分类号： H01L25/065 ,  H01L23/50 ,  H01L23/538 ,  H01L27/088

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

摘要： A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US12119349B2

公开(公告)日：2024-10-15

申请号：US17404639

申请日：2021-08-17

申请人： SOCIONEXT INC.

发明人： Hideyuki Komuro ,  Tomoya Tsuruta ,  Yasuhiro Nakaoka

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/118

CPC分类号： H01L27/092 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11807

摘要： A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

公开(公告)号：US20240332300A1

公开(公告)日：2024-10-03

申请号：US18744087

申请日：2024-06-14

申请人： Socionext Inc.

发明人： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC分类号： H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US12107592B2

公开(公告)日：2024-10-01

申请号：US17864966

申请日：2022-07-14

申请人： Socionext Inc.

发明人： Kenneth Stephen Hunt ,  Antoine Morineau ,  Aadilhussain Maniyar

IPC分类号： H03M1/06 ,  H03K5/24

CPC分类号： H03M1/0607 ,  H03K5/2481 ,  H03K5/249

摘要： A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry. The control circuitry controls the at least one offset-correction circuit to: control an amount by which the offset-correction signal is adjusted; and/or in a bypass operation, connect the input terminal of the at least one controllable offset-correction component to a bypass-operation reference voltage supply; and/or in a maintenance operation, control the charging-operation voltage supply and/or the bypass-operation voltage supply to control leakage of the charge stored on the holding capacitor.

公开(公告)号：US20240312981A1

公开(公告)日：2024-09-19

申请号：US18671451

申请日：2024-05-22

申请人： Socionext Inc.

发明人： Yoshito UCHIHASHI ,  Masahiro GION ,  Toshihiro NAKAMURA

IPC分类号： H01L27/02

CPC分类号： H01L27/0285

摘要： An ESD protection circuit includes: a protective element placed between VDD and VSS; an RC circuit; and an inverter connected to a node of the RC circuit at its input and to a node of the protective element at its output. The inverter includes a PMOS connected to VDD at its source and an NMOS connected to VSS at its source. The PMOS and the NMOS are connected in common to the node of the RC circuit at their gates and to the node of the protective element at their drains. The gate length of the PMOS is smaller than the gate length of the NMOS.

公开(公告)号：US20240310864A1

公开(公告)日：2024-09-19

申请号：US18668961

申请日：2024-05-20

申请人： Socionext Inc.

发明人： Yishen HU

IPC分类号： G05F3/26

CPC分类号： G05F3/262

摘要： A current mirror circuit includes: a plurality of first transistors connected to a first power supply at their sources and to an input terminal at their gates and drains; and a second transistor connected to the first power supply at its source, to the input terminal at its gate, and to an output terminal at its drain. A switch circuit is provided between at least one of the first transistors and the input terminal. The switch circuit includes third and fourth transistors connected in series between the first transistor and the input terminal, an inverter circuit, and a fifth transistor connected between a middle node of the third and fourth transistors and an 10 output terminal of the inverter circuit. A switch control signal is given to the gates of the third to fifth transistors and to the input of the inverter circuit.

公开(公告)号：US12081219B2

公开(公告)日：2024-09-03

申请号：US18318303

申请日：2023-05-16

申请人： Socionext Inc.

发明人： Takuya Fujimura

IPC分类号： H03K5/13 ,  H03D7/00 ,  H04L25/03

CPC分类号： H03K5/13 ,  H03D7/00 ,  H04L25/03057

摘要： A phase interpolation circuit includes: a first buffer circuit configured to adjust a rise time or a fall time of a first reference clock signal based on a first control signal to generate a first input clock signal; a second buffer circuit configured to adjust a rise time or a fall time of a second reference clock signal based on a second control signal to generate a second input clock signal; a detection circuit configured to detect a rise time or a fall time of the first input clock signal or the second input clock signal and generate the first control signal and the second control signal according to a detection result thereof; and a mixer circuit configured to generate an output clock signal having a phase between a phase of the first input clock signal and a phase of the second input clock signal.

公开(公告)号：US20240234412A1

公开(公告)日：2024-07-11

申请号：US18611332

申请日：2024-03-20

申请人： Socionext Inc.

发明人： Kazuya OKUBO

IPC分类号： H01L27/02 ,  H01L23/528 ,  H01L23/60

CPC分类号： H01L27/0292 ,  H01L23/5286 ,  H01L23/60

摘要： A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.

公开(公告)号：US12025423B2

公开(公告)日：2024-07-02

申请号：US17381071

申请日：2021-07-20

申请人： SOCIONEXT INC.

发明人： Yuya Tagami

IPC分类号： G01B11/03 ,  G03B15/00 ,  G06T7/73 ,  G06T7/80 ,  H04N23/60

CPC分类号： G01B11/03 ,  G03B15/00 ,  G06T7/74 ,  G06T7/80 ,  H04N23/60 ,  G06T2207/30208 ,  H04N2201/3205 ,  H04N2201/3253

摘要： A camera information calculation device includes a hardware processor. The hardware processor functions as a first calculation unit and a second calculation unit. The first calculation unit calculates, based on a first image and a first video, first camera positional information indicating a position of a first camera. The first image includes a first object taken by the first camera. The first video includes the first object taken by a third camera. The second calculation unit calculates, based on a second image and a second video, second camera positional information indicating a position of a second camera disposed away from the first camera. The second image includes a second object taken by the second camera. The second video includes the second object taken by the third camera.