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公开(公告)号:US20230208407A1
公开(公告)日:2023-06-29
申请号:US18177558
申请日:2023-03-02
申请人: SOCIONEXT INC.
发明人: Masahisa IIDA , Masahiro GION
IPC分类号: H03K3/356 , H03K19/003 , H03K19/0185
CPC分类号: H03K3/356017 , H03K19/00315 , H03K19/018507
摘要: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.
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公开(公告)号:US20180287600A1
公开(公告)日:2018-10-04
申请号:US16001199
申请日:2018-06-06
申请人: SOCIONEXT INC.
发明人: Masahisa IIDA , Masahiro GION
IPC分类号: H03K17/04 , H03K19/017 , H03K19/0175 , H03K17/687 , H03K19/0944
CPC分类号: H03K17/04 , H03K17/687 , H03K19/017 , H03K19/0175 , H03K19/017509 , H03K19/018521 , H03K19/0944
摘要: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.
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公开(公告)号:US20240312981A1
公开(公告)日:2024-09-19
申请号:US18671451
申请日:2024-05-22
申请人: Socionext Inc.
IPC分类号: H01L27/02
CPC分类号: H01L27/0285
摘要: An ESD protection circuit includes: a protective element placed between VDD and VSS; an RC circuit; and an inverter connected to a node of the RC circuit at its input and to a node of the protective element at its output. The inverter includes a PMOS connected to VDD at its source and an NMOS connected to VSS at its source. The PMOS and the NMOS are connected in common to the node of the RC circuit at their gates and to the node of the protective element at their drains. The gate length of the PMOS is smaller than the gate length of the NMOS.
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公开(公告)号:US20230132469A1
公开(公告)日:2023-05-04
申请号:US17959810
申请日:2022-10-04
申请人: Socionext Inc.
发明人: Masahiro GION
IPC分类号: H03K19/0185 , H03K3/037
摘要: A level shift circuit includes first to fourth n-type transistors, first and second p-type transistors, and first and second inverters. The first n-type transistor receives an input signal at its gate and has a drain connected to an inverted output node. The first p-type transistor is placed between a third power supply and the inverted output node. The second n-type transistor receives an inverted input signal at its gate and has a drain connected to an output node. The second p-type transistor is placed between the third power supply and the output node. The third n-type transistor is between the inverted output node and an inverted input node, and the first inverter between the drain and gate of the third n-type transistor. The fourth n-type transistor is between the output node and an input node, and the second inverter between the drain and gate of the fourth n-type transistor.
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公开(公告)号:US20210105009A1
公开(公告)日:2021-04-08
申请号:US17122737
申请日:2020-12-15
申请人: SOCIONEXT INC.
发明人: Masahisa IIDA , Masahiro GION
IPC分类号: H03K3/356 , H03K19/003 , H03K19/0185
摘要: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.
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