-
公开(公告)号：US20240322834A1
公开(公告)日：2024-09-26
申请号：US18454435
申请日：2023-08-23
发明人： John P. LESSO , Ivan PERRY , Salvatore CAPORALE , Gagan MIDHA , James WELLS
CPC分类号： H03M1/1009 , H01M6/02 , H01M6/5044 , H03M1/1071
摘要： Circuitry for processing an analyte signal obtained from an electrochemical cell, the circuitry comprising: measurement circuitry having a first measurement input coupled to a first electrode of the electrochemical cell, the measurement circuitry configured to convert the analyte signal at the first measurement input to a first analog output signal; an analog-to-digital converter (ADC) having an first ADC input for receiving the first analog output signal, the ADC configured to convert the first analog output signal to a first digital output signal at an ADC output; compensation circuitry configured in a measurement mode to: apply a first compensation to the first digital output signal to obtain a first compensated digital output signal, the first compensation to compensate for non-linearity in the ADC; and apply a second compensation to the first compensated digital output signal to obtain a second compensated digital output signal, the second compensation to compensate for non-linearity in the measurement circuitry; control circuitry configured in a calibration mode to: apply a first calibration signal at the first ADC input and adapt the first compensation based on the first calibration signal and the first compensated digital output signal; and apply a second calibration signal at the first electrode and adapt the second compensation based on the second calibration signal and the second compensated digital output signal.
-
公开(公告)号：US20240291438A1
公开(公告)日：2024-08-29
申请号：US18658837
申请日：2024-05-08
发明人： Seiji TAKEUCHI
CPC分类号： H03F1/30 , G03B13/36 , G05F3/24 , H02P25/034 , H03F3/45 , H03F2200/453 , H03M1/1009
摘要： Driver circuits, systems for driving actuators, and imaging systems with actuators. The driver circuit includes a current comparator circuit, a driver, and a replica circuit. The current comparator circuit includes a first node having a first voltage. The current comparator circuit also includes a second node having a second voltage. The driver includes a first terminal responsive to the second voltage. The driver also includes a second terminal connected to a reference voltage. The replica circuit includes a third terminal connected to the first node. The replica circuit also includes a fourth terminal connected to the second terminal of the driver. The replica circuit also includes a fifth terminal connected to the first terminal of the driver.
-
公开(公告)号：US11881969B2
公开(公告)日：2024-01-23
申请号：US17885001
申请日：2022-08-10
发明人： Anup P Jose , Sam Ray , Ali Fazli Yeknami , Amir Amirkhany
CPC分类号： H04L25/0292 , H03M1/1009 , H04L25/028 , H04L25/03878 , H04L27/0002
摘要： A receiver for a serial data link, including an analog front end (AFE) including a continuous-time linear equalizer (CTLE) configured to receive an input signal from a transmitter, the CTLE including a first output node; a second output node; a plurality of programmable tail current sources configured to adjust a direct current (DC) offset between the first output node and the second output node; and a calibration circuit including: a slicer configured to output a difference between a first average output voltage corresponding to the first output node and a second average output, voltage corresponding to the second output node; and a calibration counter configured to increment or decrement an offset count based on the difference, wherein the plurality of programmable tail current sources are adjusted based on a value of the offset count.
-
公开(公告)号：US20230412186A1
公开(公告)日：2023-12-21
申请号：US18461152
申请日：2023-09-05
CPC分类号： H03M1/502 , H03M1/1009 , H03M1/362
摘要： In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
-
公开(公告)号：US20230387865A1
公开(公告)日：2023-11-30
申请号：US18450123
申请日：2023-08-15
发明人： Seiji TAKEUCHI
IPC分类号： H03F1/30 , G03B13/36 , G05F3/24 , H03F3/45 , H02P25/034
CPC分类号： H03F1/30 , G03B13/36 , G05F3/24 , H03F3/45 , H02P25/034 , H03F2200/453 , H03M1/1009
摘要： Driver circuits, systems for driving actuators, and imaging systems with actuators. The driver circuit includes a current comparator circuit, a driver, and a replica circuit. The current comparator circuit includes a first node having a first voltage. The current comparator circuit also includes a second node having a second voltage. The driver includes a first terminal responsive to the second voltage. The driver also includes a second terminal connected to a reference voltage. The replica circuit includes a third terminal connected to the first node. The replica circuit also includes a fourth terminal connected to the second terminal of the driver. The replica circuit also includes a fifth terminal connected to the first terminal of the driver.
-
公开(公告)号：US11831319B2
公开(公告)日：2023-11-28
申请号：US17714520
申请日：2022-04-06
发明人： Rong Wu , Wenliang Ren , Yin Tang
CPC分类号： H03K5/02 , H03K5/24 , H03M1/1009 , H03M3/30 , H03K17/16
摘要： Disclosed are a readout circuit, an offset voltage eliminating method and device, a computer device, and a non-transitory computer-readable storage medium. The readout circuit includes an object quantizer and an offset voltage elimination circuit. The offset voltage elimination circuit includes a correction circuit and a calibration circuit, an input of the correction circuit is connected to an output of the object quantizer, a compensation input of the calibration circuit is connected to an output of the current compensator, and a reference input of the calibration circuit is connected to the output of the object quantizer.
-
公开(公告)号：US20230344681A1
公开(公告)日：2023-10-26
申请号：US17885001
申请日：2022-08-10
发明人： Anup P. JOSE , Sam RAY , Ali FAZLI YEKNAMI , Amir AMIRKHANY
CPC分类号： H04L25/0292 , H04L25/03878 , H04L27/0002 , H03M1/1009 , H04L25/028
摘要： A receiver for a serial data link, including an analog front end (AFE) including a continuous-time linear equalizer (CTLE) configured to receive an input signal from a transmitter, the CTLE including a first output node; a second output node; a plurality of programmable tail current sources configured to adjust a direct current (DC) offset between the first output node and the second output node; and a calibration circuit including: a slicer configured to output a difference between a first average output voltage corresponding to the first output node and a second average output, voltage corresponding to the second output node; and a calibration counter configured to increment or decrement an offset count based on the difference, wherein the plurality of programmable tail current sources are adjusted based on a value of the offset count.
-
公开(公告)号：US11784654B2
公开(公告)日：2023-10-10
申请号：US17691502
申请日：2022-03-10
CPC分类号： H03M1/1009 , H03M1/1071 , H03M1/10 , H03M1/66 , H03M7/00
摘要： The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.
-
公开(公告)号：US20230238977A1
公开(公告)日：2023-07-27
申请号：US17694606
申请日：2022-03-14
发明人： Da Wei , Ali Fazli Yeknami
CPC分类号： H03M1/1009 , H03M1/0617 , H03K5/08
摘要： A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.
-
10.发明申请公开(公告)号：US20190245551A1
公开(公告)日：2019-08-08
申请号：US16386188
申请日：2019-04-16
申请人： Avnera Corporation
发明人： Jianping Wen , Gordon Ueki
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/1038 , H03M1/462 , H03M1/466
摘要： The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.
-
-
-
-
-
-
-
-
-
搜索结果
542 条记录 (耗时 0.022 秒)
