MULTI-PURPOSE COMPENSATION CIRCUITS FOR HIGH-SPEED RECEIVERS

    公开(公告)号:US20230238977A1

    公开(公告)日:2023-07-27

    申请号:US17694606

    申请日:2022-03-14

    CPC classification number: H03M1/1009 H03M1/0617 H03K5/08

    Abstract: A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

    WIDE COMMON MODE HIGH RESOLUTION COMPARATOR
    3.
    发明申请

    公开(公告)号:US20190286178A1

    公开(公告)日:2019-09-19

    申请号:US16057124

    申请日:2018-08-07

    Abstract: A comparator. The comparator includes two back-to-back inverters, a differential pair, and a first common mode compensation transistor. The differential pair has two outputs configured to receive respective series currents from, or supply respective series currents to, the back-to-back inverters. The first common mode compensation transistor is configured to supply a compensating current to, or draw a compensating current from, a first output of the two outputs of the differential pair.

    Power efficient slicer for decision feedback equalizer

    公开(公告)号:US11973621B2

    公开(公告)日:2024-04-30

    申请号:US17683204

    申请日:2022-02-28

    Inventor: Da Wei

    CPC classification number: H04L25/03057

    Abstract: A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.

    Multi-purpose compensation circuits for high-speed receivers

    公开(公告)号:US12199627B2

    公开(公告)日:2025-01-14

    申请号:US17694606

    申请日:2022-03-14

    Abstract: A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

    MULTI-PURPOSE COMPENSATION CIRCUITS FOR HIGH-SPEED RECEIVERS

    公开(公告)号:US20250150087A1

    公开(公告)日:2025-05-08

    申请号:US19019354

    申请日:2025-01-13

    Abstract: A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

    POWER EFFICIENT SLICER FOR DECISION FEEDBACK EQUALIZER

    公开(公告)号:US20230198816A1

    公开(公告)日:2023-06-22

    申请号:US17683204

    申请日:2022-02-28

    Inventor: Da Wei

    CPC classification number: H04L25/03057 H03F3/193 H03F2200/451

    Abstract: A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.

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