Abstract:
A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption.
Abstract:
A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.
Abstract:
A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.
Abstract:
An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.
Abstract:
A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
Abstract:
A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.
Abstract:
An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.
Abstract:
A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.
Abstract:
An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.
Abstract:
An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.