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公开(公告)号:US12095601B2
公开(公告)日:2024-09-17
申请号:US18064593
申请日:2022-12-12
Applicant: STMicroelectronics International N.V.
Inventor: Andrea Mineo , Giovanni Amedeo Cirillo
IPC: H04L27/06
CPC classification number: H04L27/06
Abstract: According to an embodiment, a circuit for decoding a biphase mark coding (BMC) encoded signal is provided. The circuit includes a matched filter, a decoder circuit and a finite state machine (FSM) circuit. The matched filter is configured to generate a first response and a second response to the BMC encoded signal. The first response and second response operate respectively, at a half clock period and a full clock period of the BMC encoded signal. The detector circuit is coupled to an output of the matched filter. The detector circuit is configured to generate an output signal based on detecting a half-bit rise for the first response, a half-bit fall for the first response, a full-bit rise for the second response, or a full-bit fall for the second response. The FSM circuit is configured to decode the BMC encoded signal based on the output signal of the detector circuit.
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公开(公告)号:US20240243954A1
公开(公告)日:2024-07-18
申请号:US18155999
申请日:2023-01-18
Applicant: Renesas Electronics America Inc.
Inventor: Tetsuo SATO , Jiang CHEN , Qiu SHA
CPC classification number: H04L27/06 , H01L23/66 , H04L25/0266 , H01L2223/6611
Abstract: Systems, devices, and methods for isolating digital signals are described. A carrier signal can be modulated using a first signal to generate a first modulated signal. The carrier signal and the first modulated signal can be transmitted through a forward path in an isolation barrier, where transmitting the carrier signal through the isolation barrier can transform the carrier signal into a delayed carrier signal. The first modulated signal can be demodulated to recover the first signal. The delayed carrier signal can be modulated using a second signal to generate a second modulated signal. The delayed carrier signal and the second modulated signal can be transmitted through a return path in the isolation barrier, where the return path and the forward path has opposite directions.
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公开(公告)号:US20240223024A1
公开(公告)日:2024-07-04
申请号:US18487473
申请日:2023-10-16
Applicant: NuCurrent, Inc.
Inventor: Alberto Peralta , Michael Katz , Md. Nazmul Alam
Abstract: A wireless receiver system includes a receiver antenna, a sensor, a demodulation circuit, and a receiver controller. The sensor is configured to detect electrical information associated with AC wireless signals, the electrical information including, at least, a voltage of the AC wireless signals. The demodulation circuit is configured to receive the electrical information from the at least one sensor, detect a change in the electrical information, determine if the change in the electrical information meets or exceeds one of a rise threshold or a fall threshold, if the change exceeds one of the rise threshold or the fall threshold, generate an alert, and output a plurality of data alerts. The receiver controller is configured to receive the plurality of data alerts from the demodulation circuit, and decode the plurality of data alerts into the wireless data signals.
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公开(公告)号:US11888654B2
公开(公告)日:2024-01-30
申请号:US17898851
申请日:2022-08-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jueon Kim , Taehyoung Kim , Seungjin Park , Jihwan Hyun , Myoungbo Kwak , Junghwan Choi
CPC classification number: H04L25/03006 , G01R31/31703 , H03K5/24 , H03K9/02 , H03K21/08 , H04B17/21 , H04L27/06
Abstract: An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.
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公开(公告)号:US11862994B2
公开(公告)日:2024-01-02
申请号:US17717701
申请日:2022-04-11
Applicant: NuCurrent, Inc.
Inventor: Alberto Peralta , Michael Katz , Md. Nazmul Alam
CPC classification number: H02J50/80 , H02J50/12 , H04B5/0037 , H04L27/06 , H04B5/0081
Abstract: A wireless transmission system includes a transmitter antenna, a sensor, a demodulation circuit, and a transmitter controller. The sensor is configured to detect electrical information associated with AC wireless signals, the electrical information including, at least, a voltage of the AC wireless signals. The demodulation circuit is configured to receive the electrical information from the at least one sensor, detect a change in the electrical information, determine if the change in the electrical information meets or exceeds one of a rise threshold or a fall threshold, if the change exceeds one of the rise threshold or the fall threshold, generate an alert, and output a plurality of data alerts. The transmitter controller is configured to receive the plurality of data alerts from the demodulation circuit, and decode the plurality of data alerts into the wireless data signals.
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公开(公告)号:US20230370115A1
公开(公告)日:2023-11-16
申请号:US18160532
申请日:2023-01-27
Applicant: Apple Inc.
Inventor: Adam L. Schwartz , Sriram Narayanan , Xing Zhou
CPC classification number: H04B5/0037 , H02J50/10 , H02J50/80 , H04B5/0031 , H04L27/06
Abstract: A wireless power system has a wireless power transmitting device and a wireless power receiving device. The wireless power transmitting device may include ASK decoding circuitry. An inverter controller may supply control signals to an inverter based on a clock signal. To improve wireless transmission at various frequencies of interest, the clock signal used by the inverter controller may be dithered using a modulating signal. To mitigate bit errors in ASK decoding caused by the dithering of the clock signal in the wireless power transmitting device, ASK communication receiving circuitry in the wireless power transmitting device may receive information regarding the modulating signal used to dither the clock signal. The ASK communication receiving circuitry may receive a clock signal that has been dithered using the modulating signal, dither an analog-to-digital converter sampling rate using the modulating signal, or include notch filtering circuitry with parameters determined based on the modulating signal.
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公开(公告)号:US20230361796A1
公开(公告)日:2023-11-09
申请号:US18352424
申请日:2023-07-14
Applicant: STMicroelectronics S.r.l.
Inventor: Nunzio Spina , Giuseppe Palmisano , Alessandro Castorina
CPC classification number: H04B1/16 , H04L27/06 , H03F3/19 , H03F3/245 , H03F2200/451
Abstract: A method for calibrating the DC operating point of a PWM receiver circuit is disclosed. The PWM receiving circuit includes an envelope detector having a first resistor string, and includes a bias circuit having a second resistor string and a plurality of switches. The second resistor string is coupled between a supply voltage and a reference voltage and functions as a voltage divider. Each switch, when closed, accesses a second voltage at a node of the second resistor string connected to the closed switch. To perform the calibration process, the plurality of switches is closed one at a time, and the second voltage is compared with a first voltage at a first node of the first resistor string. The switch that, when closed, produces the smallest difference between the first voltage and the second voltage remains closed after the calibration process, and is used for demodulating the PWM signal.
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公开(公告)号:US20230254188A1
公开(公告)日:2023-08-10
申请号:US17650572
申请日:2022-02-10
Applicant: CREDO TECHNOLOGY GROUP LTD
Inventor: FANG CAI , JUNQING (PHIL) SUN , HAOLI QIAN
CPC classification number: H04L27/06 , H04L7/0012
Abstract: Accordingly, there are disclosed herein receivers and receiving methods that provide a graceful transition from PAM2 to PAM4 signaling. One illustrative method includes: negotiating a link speed having PAM4 signaling; performing adaption of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling said adaptation before said switching to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling said adaptation after PAM4 signaling is detected. Another illustrative method includes: negotiating a link speed having PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for a change in at least one signal characteristic while performing PAM2 detection; and transitioning to PAM4 detection after detecting said change.
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公开(公告)号:US11716674B2
公开(公告)日:2023-08-01
申请号:US17407478
申请日:2021-08-20
Applicant: ZTE Corporation
Inventor: Xing Liu , Peng Hao , Ting Miao , Haigang He , Feng Bi
CPC classification number: H04W48/12 , H04L5/0053 , H04L27/06 , H04L27/2613 , H04W56/002 , H04W48/16
Abstract: The described technology can be implemented as a wireless communication method in which timing information in a wireless communication network is mapped to a signal. The timing information includes information related to a synchronization signal block index and the signal includes at least one of a reference signal on a broadcast channel and a synchronization signal. The signal is transmitted by including at least a part of the information related to the synchronization signal block index.
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公开(公告)号:US11683057B2
公开(公告)日:2023-06-20
申请号:US17527631
申请日:2021-11-16
Applicant: Rambus Inc.
Inventor: Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
CPC classification number: H04B1/123 , H04B1/12 , H04L25/0264 , H04L25/03057 , H04L25/03076 , H04L25/03133 , H04L25/4917 , H04L27/00 , H04L27/01 , H04L27/06
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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