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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12080379B2

    公开(公告)日：2024-09-03

    申请号：US17939016

    申请日：2022-09-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

    Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

    Receiver including offset compensation circuit
    5.
    发明授权
    Receiver including offset compensation circuit 有权

    公开(公告)号：US11817861B2

    公开(公告)日：2023-11-14

    申请号：US17898631

    申请日：2022-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Seungjin Park ,  Jihwan Hyun ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03K5/00 ,  H03K5/01 ,  H03K5/003 ,  H03K5/24 ,  H03K5/05

    CPC classification number: H03K5/01 ,  H03K5/003 ,  H03K5/05 ,  H03K5/24

    Abstract: A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240395298A1

    公开(公告)日：2024-11-28

    申请号：US18794825

    申请日：2024-08-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

    IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

    Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

    VOLTAGE REGULATORS
    8.
    发明申请
    VOLTAGE REGULATORS 有权

    公开(公告)号：US20250155911A1

    公开(公告)日：2025-05-15

    申请号：US18756948

    申请日：2024-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chaekang Lim ,  Youngwoo Park ,  Seungjin Park ,  Jindo Byun ,  Seunghoon Lee ,  Youngdon Choi

    IPC: G05F1/575

    Abstract: A voltage regulator includes a pass transistor generating an output voltage in response to a gate voltage, and an error amplifier circuit outputting the gate voltage. The error amplifier circuit includes a first input terminal receiving a first reference voltage level from a reference voltage generator, a second input terminal receiving a second reference voltage level from the reference voltage generator, a third input terminal receiving a first voltage level of a first end of a target circuit, a fourth input terminal receiving a second voltage level of a second end of the target circuit, and an output terminal that outputs the gate voltage generated based on the first reference voltage level, the second reference voltage level, the first voltage level, and the second voltage level. A potential difference of the first voltage level and the second voltage level is an operating voltage of the target circuit.

    RECEIVER INCLUDING OFFSET COMPENSATION CIRCUIT
    10.
    发明公开
    RECEIVER INCLUDING OFFSET COMPENSATION CIRCUIT 审中-公开

    公开(公告)号：US20230170887A1

    公开(公告)日：2023-06-01

    申请号：US17898631

    申请日：2022-08-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jueon Kim ,  Taehyoung Kim ,  Seungjin Park ,  Jihwan Hyun ,  Myoungbo Kwak ,  Junghwan Choi

    IPC: H03K5/01 ,  H03K5/24 ,  H03K5/003

    CPC classification number: H03K5/01 ,  H03K5/24 ,  H03K5/003

    Abstract: A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

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