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    Multi-purpose compensation circuits for high-speed receivers
    1.
    发明授权
    Multi-purpose compensation circuits for high-speed receivers 有权

    公开(公告)号：US12199627B2

    公开(公告)日：2025-01-14

    申请号：US17694606

    申请日：2022-03-14

    Applicant: Samsung Display Co., Ltd.

    Inventor： Da Wei ,  Ali Fazli Yeknami

    IPC: H03K5/08 ,  H03M1/06 ,  H03M1/10

    Abstract: A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

    TWO-DOMAIN TWO-STAGE SENSING FRONT-END CIRCUITS AND SYSTEMS
    3.
    发明申请
    TWO-DOMAIN TWO-STAGE SENSING FRONT-END CIRCUITS AND SYSTEMS 有权

    公开(公告)号：US20220120805A1

    公开(公告)日：2022-04-21

    申请号：US17168093

    申请日：2021-02-04

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ali Fazli Yeknami ,  Younghoon Song

    IPC: G01R31/26 ,  H03F3/45

    Abstract: A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

    MULTI-PURPOSE COMPENSATION CIRCUITS FOR HIGH-SPEED RECEIVERS
    4.
    发明申请
    MULTI-PURPOSE COMPENSATION CIRCUITS FOR HIGH-SPEED RECEIVERS 有权

    公开(公告)号：US20250150087A1

    公开(公告)日：2025-05-08

    申请号：US19019354

    申请日：2025-01-13

    Applicant: Samsung Display Co., Ltd.

    Inventor： Da Wei ,  Ali Fazli Yeknami

    IPC: H03M1/10 ,  H03K5/08 ,  H03M1/06

    Abstract: A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

    Two-domain two-stage sensing front-end circuits and systems
    5.
    发明授权
    Two-domain two-stage sensing front-end circuits and systems 有权

    公开(公告)号：US12196801B2

    公开(公告)日：2025-01-14

    申请号：US18093669

    申请日：2023-01-05

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ali Fazli Yeknami ,  Younghoon Song

    IPC: G01R31/26 ,  H03F3/45

    Abstract: A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

    Real-time DC-balance aware AFE offset cancellation
    7.
    发明授权
    Real-time DC-balance aware AFE offset cancellation 有权

    公开(公告)号：US11881969B2

    公开(公告)日：2024-01-23

    申请号：US17885001

    申请日：2022-08-10

    Applicant: Samsung Display Co., Ltd.

    Inventor： Anup P Jose ,  Sam Ray ,  Ali Fazli Yeknami ,  Amir Amirkhany

    IPC: H04L25/02 ,  H04L25/03 ,  H03M1/10 ,  H04L27/00

    CPC classification number: H04L25/0292 ,  H03M1/1009 ,  H04L25/028 ,  H04L25/03878 ,  H04L27/0002

    Abstract: A receiver for a serial data link, including an analog front end (AFE) including a continuous-time linear equalizer (CTLE) configured to receive an input signal from a transmitter, the CTLE including a first output node; a second output node; a plurality of programmable tail current sources configured to adjust a direct current (DC) offset between the first output node and the second output node; and a calibration circuit including: a slicer configured to output a difference between a first average output voltage corresponding to the first output node and a second average output, voltage corresponding to the second output node; and a calibration counter configured to increment or decrement an offset count based on the difference, wherein the plurality of programmable tail current sources are adjusted based on a value of the offset count.

    CONTINUOUS TIME LINEAR EQUALIZATION (CTLE) FEEDBACK FOR TUNABLE DC GAIN AND MID-BAND CORRECTION
    8.
    发明公开
    CONTINUOUS TIME LINEAR EQUALIZATION (CTLE) FEEDBACK FOR TUNABLE DC GAIN AND MID-BAND CORRECTION 审中-公开

    公开(公告)号：US20230268896A1

    公开(公告)日：2023-08-24

    申请号：US17725392

    申请日：2022-04-20

    Applicant: Samsung Display co,Ltd.

    Inventor： Ali Fazli Yeknami ,  Anup P. Jose

    IPC: H03F3/45 ,  H04B1/04

    CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H04B1/0458 ,  H04B2001/0433

    Abstract: An analog front end (AFE) circuit including: a continuous time linear equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit including: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; the second output of the feedback circuit is connected to a first input of the TIA.

    MULTI-PURPOSE COMPENSATION CIRCUITS FOR HIGH-SPEED RECEIVERS
    9.
    发明公开
    MULTI-PURPOSE COMPENSATION CIRCUITS FOR HIGH-SPEED RECEIVERS 审中-公开

    公开(公告)号：US20230238977A1

    公开(公告)日：2023-07-27

    申请号：US17694606

    申请日：2022-03-14

    Applicant: Samsung Display Co., Ltd.

    Inventor： Da Wei ,  Ali Fazli Yeknami

    IPC: H03M1/10 ,  H03M1/06 ,  H03K5/08

    CPC classification number: H03M1/1009 ,  H03M1/0617 ,  H03K5/08

    Abstract: A device includes a first compensation circuit configured to adjust an analog front end (AFE) output to generate a first adjusted AFE output, a first data slicer configured to output a first voltage based on the first adjusted AFE output. The first compensation circuit includes a first path between a voltage source and a ground, including a first transistor, a first adjustable current source, a first input voltage node configured to receive the AFE output, and a first output voltage node coupled to the first data slicer, a second path between the voltage source and the ground, including a second transistor, a second adjustable current source, a second input voltage node configured to receive the AFE output, and a second output voltage node coupled to the second data slicer, and a configurable resistance resistor and a configurable capacitance capacitor coupled in parallel across the first path and the second path.

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