Clock data recovery (CDR) with multiple proportional path controls

    公开(公告)号:US11870880B2

    公开(公告)日:2024-01-09

    申请号:US17714104

    申请日:2022-04-05

    CPC classification number: H04L7/0016 H03L7/085 H03L7/0807 H03L7/099 H03M1/66

    Abstract: A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

    CLOCK DATA RECOVERY (CDR) WITH MULTIPLE PROPORTIONAL PATH CONTROLS

    公开(公告)号:US20230246800A1

    公开(公告)日:2023-08-03

    申请号:US17714104

    申请日:2022-04-05

    CPC classification number: H04L7/0016 H03L7/0807 H03L7/085 H03M1/66 H03L7/099

    Abstract: A digital clock data recovery circuit including: a first vote circuit connected at an output of a first deserializer and configured to generate an even up/down signal based on even deserialized signals from the first deserializer; a first digital to analog converter (DAC) connected at an output of the first vote circuit and configured to control a voltage and/or frequency of a voltage controlled oscillator (VCO) based on the even up/down signal from the first vote circuit; a second vote circuit connected at an output of a second deserializer and configured to generate an odd up/down signal based on odd deserialized signals from the second deserializer; and a second DAC connected at an output of the second vote circuit and configured to control the voltage and/or frequency of the VCO based on the odd up/down signal from the second vote circuit.

    Reference signal generation by reusing the driver circuit

    公开(公告)号:US11081064B1

    公开(公告)日:2021-08-03

    申请号:US16869546

    申请日:2020-05-07

    Abstract: A display compensation circuit includes a driver circuit including a digital-to-analog converter (DAC), the driver circuit configured to drive pixels of a display panel; and a compensation circuit including a current-mode sensing circuit and a reference current generator circuit, the compensation circuit configured to determine a value to compensate for pixel variations across the display panel, the reference current generator circuit configured to generate a reference current using the DAC of the driver circuit.

    REFERENCE SIGNAL GENERATION BY REUSING THE DRIVER CIRCUIT

    公开(公告)号:US20210217367A1

    公开(公告)日:2021-07-15

    申请号:US16869546

    申请日:2020-05-07

    Abstract: A display compensation circuit includes a driver circuit including a digital-to-analog converter (DAC), the driver circuit configured to drive pixels of a display panel; and a compensation circuit including a current-mode sensing circuit and a reference current generator circuit, the compensation circuit configured to determine a value to compensate for pixel variations across the display panel, the reference current generator circuit configured to generate a reference current using the DAC of the driver circuit.

    Two-domain two-stage sensing front-end circuits and systems

    公开(公告)号:US12196801B2

    公开(公告)日:2025-01-14

    申请号:US18093669

    申请日:2023-01-05

    Abstract: A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

    TWO-DOMAIN TWO-STAGE SENSING FRONT-END CIRCUITS AND SYSTEMS

    公开(公告)号:US20220120805A1

    公开(公告)日:2022-04-21

    申请号:US17168093

    申请日:2021-02-04

    Abstract: A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

    Replica pixel for stand-alone test of display driver

    公开(公告)号:US11341879B2

    公开(公告)日:2022-05-24

    申请号:US17185237

    申请日:2021-02-25

    Abstract: A replica pixel for testing a display IC that includes a driving circuit that drives a display panel and a sensing circuit that senses a received current is presented. The replica pixel includes a replica pixel transistor, which has a first terminal switchably coupled to a power source, a gate coupled to a first node of a capacitor, and a second terminal coupled to a second node of the capacitor. The first node of the capacitor is switchably coupled to a reference voltage Vref. The second node of the capacitor is switchably coupled to a coupling node, wherein the coupling node selectively couples to either the driving circuit or the sensing circuit. The replica pixel is approximately a real pixel without the display element, and may be used to test the display IC without assembling the display IC with a display panel.

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