公开(公告)号：US12113885B2

公开(公告)日：2024-10-08

申请号：US17186476

申请日：2021-02-26

申请人： TUSIMPLE, INC. ,  BEIJING TUSEN ZHITU TECHNOLOGY CO., LTD.

发明人： Xiaoling Han ,  Junjun Xin ,  Lei Nie ,  Yue Pan ,  Yu Zhang ,  Jade E. Day ,  Zehua Huang ,  Esayas Naizghi ,  Pingyuan Ji ,  Zhiqi Gong

IPC分类号： H04L7/00 ,  G01C21/16 ,  G01C21/28 ,  G01S17/931 ,  G01S19/01 ,  H04L67/12

CPC分类号： H04L7/0016 ,  G01C21/16 ,  G01C21/28 ,  G01S17/931 ,  G01S19/01 ,  H04L67/12

摘要： Devices, systems, and methods for hardware-based time synchronization for heterogenous sensors are described. An example method includes generating a plurality of input trigger pulses having a nominal pulse-per-second (PPS) rate, generating, based on timing information derived from the plurality of input trigger pulses, a plurality of output trigger pulses, and transmitting the plurality of output trigger pulses to a sensor of a plurality of sensors, wherein a frequency of the plurality of output trigger pulses corresponds to a target operating frequency of the sensor, wherein, in a case that a navigation system coupled to the synchronization unit is functioning correctly, the plurality of input trigger pulses is generated based on a nominal PPS signal from the navigation unit, and wherein, in a case that the navigation system is not functioning correctly, the plurality of input trigger pulses is generated based on a simulated clock source of the synchronization unit.

公开(公告)号：US12081643B2

公开(公告)日：2024-09-03

申请号：US17590621

申请日：2022-02-01

申请人： ZaiNar, Inc.

发明人： Philip A. Kratz ,  Mainak Chowdhury ,  Alexander Hooshmand ,  Daniel M. Jacker

IPC分类号： H04L7/00 ,  H04L7/04 ,  H04L7/08 ,  H04W64/00

CPC分类号： H04L7/08 ,  H04L7/0016 ,  H04L7/041 ,  H04W64/003

摘要： A method includes, at a first node: transmitting a first synchronization signal at a first time according to a first clock of the first node; back-coupling the first synchronization signal to generate a first self-receive signal; calculating a time-of-arrival of the first self-receive signal according to the first clock; and calculating a time-of-arrival of the second synchronization signal according to the first clock. The method also includes, at the second node: transmitting the second synchronization signal at a second time according to a second clock of the second node; back-coupling the second synchronization signal to generate a second self-receive signal; calculating a time-of-arrival of the second self-receive signal according to the second clock; and calculating a time-of-arrival of the first synchronization signal according to the second clock. The method S100 further includes calculating a time bias and a propagation delay between the pair of nodes based on the time-of-arrivals.

公开(公告)号：US12052309B1

公开(公告)日：2024-07-30

申请号：US17956150

申请日：2022-09-29

申请人： Open Sesame Media, Inc.

发明人： Julian McCrea ,  Timothy R. Fox ,  Douglas Warner ,  Stephen Lyons

IPC分类号： H04L65/75 ,  G06F3/16 ,  H04L1/00 ,  H04L7/00 ,  H04L47/12

CPC分类号： H04L65/765 ,  G06F3/162 ,  G06F3/165 ,  H04L1/0033 ,  H04L7/0016 ,  H04L47/12

摘要： An apparatus has an audio receiver to receive audio input from client devices. An audio transmitter transmits audio output to the client devices. A synchronicity service evaluates the audio input with respect to a set of network metrics and dynamically adjusts audio communication parameters to insure that the audio output to the client devices has a latency at or below 66 ms.

公开(公告)号：US12047483B1

公开(公告)日：2024-07-23

申请号：US18145190

申请日：2022-12-22

申请人： Marvell Asia Pte Ltd

发明人： Luca Vercesi ,  Fernando De Bernardinis

IPC分类号： H04L7/033 ,  H04L7/00

CPC分类号： H04L7/0331 ,  H04L7/0016

摘要： A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

公开(公告)号：US20240235803A9

公开(公告)日：2024-07-11

申请号：US17971650

申请日：2022-10-24

申请人： MediaTek Singapore Pte. Ltd.

发明人： Tze Yee Sin ,  Chin-Heng Leow

IPC分类号： H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0016 ,  H04L7/0331

摘要： A push-start crystal oscillator (XO), an associated electronic device and a push-start method for performing a start-up procedure of an XO are provided. The push-start XO includes an inverting amplifier and a push-start logic control circuit, wherein the inverting amplifier is coupled to a crystal load. The inverting amplifier generates a first XO signal and a second XO signal. The push-start logic control circuit receives a feedback clock from a phase locked loop (PLL), and generates a phase control clock according to the feedback clock, wherein a push phase and a settle phase are specified by the phase control clock. During the settle phase, the PLL calibrates a frequency of the feedback clock according to the second XO signal. During the push phase, the feedback clock is transmitted to the inverting amplifier in order to increase the amplitude of the first XO signal.

公开(公告)号：US20240089154A1

公开(公告)日：2024-03-14

申请号：US17931096

申请日：2022-09-09

申请人： Apple Inc.

发明人： Bo Sun ,  Jafar Savoj

IPC分类号： H04L25/03 ,  H04L7/00

CPC分类号： H04L25/03038 ,  H04L7/0016

摘要： A receiver with feed-forward equalization is disclosed. A receiver includes a delay circuit configured to receive a first signal that encodes a serial data stream having a plurality of data symbols. The delay circuit includes at least one T-coil circuit and is configured to generate a plurality of delayed signals using the first signal. The receiver further includes a front-end circuit configured to generate an equalized signal using the at first signal and one or more delayed signals of the plurality of delayed signals. A sample circuit is configured to sample the equalized signal to generate a plurality of samples. A recovery circuit configured to generate a plurality of recovered data symbols using the plurality of samples.

公开(公告)号：US11838397B2

公开(公告)日：2023-12-05

申请号：US17350758

申请日：2021-06-17

申请人： Brian R. Konigsburg

发明人： Brian R. Konigsburg

IPC分类号： H04L7/00

CPC分类号： H04L7/0016 ,  H04L7/0004 ,  H04L7/0079

摘要： In an example, a synchronization signal can be transmitted to a plurality of synchronizers. The plurality of synchronizers can include a plurality of upstream synchronizers and a downstream synchronizer. Each synchronizer of the plurality of upstream synchronizers can be caused to count from a respective count value until a predetermined end count sequence value in response to receiving the synchronization signal. The respective count value stored at each synchronizer can be representative of a difference in time between a respective upstream synchronizer of the plurality of upstream synchronizers receiving the synchronization signal and the downstream synchronizer receiving the synchronization signal. A respective processing element of a plurality of processing elements can be caused to start a respective function or operation in response to a respective upstream synchronizer reaching the predetermined end count sequence value.

公开(公告)号：US11818240B2

公开(公告)日：2023-11-14

申请号：US17547378

申请日：2021-12-10

申请人： Korea Electronics Technology Institute ,  Seoul National University R&DB Foundation

发明人： Ha Ram Ju ,  Sung Ho Lee ,  Deog Kyoon Jeong

IPC分类号： H04L7/02 ,  H04L7/00 ,  H03L7/091

CPC分类号： H04L7/0016 ,  H03L7/091 ,  H04L7/0054 ,  H04L7/0079

摘要： There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

公开(公告)号：US20230353339A1

公开(公告)日：2023-11-02

申请号：US18311129

申请日：2023-05-02

申请人： Apple Inc.

发明人： Christopher D. Finan ,  Alexander Ukanwa ,  Charles F. Dominguez ,  Jean-Didier Allegrucci ,  Jeffrey J. Irwin ,  Kalpana Bansal ,  Michael Bekerman ,  Remi Clavel

IPC分类号： H04L7/00 ,  G06F1/12

CPC分类号： H04L7/0016 ,  H04L7/0008 ,  G06F1/12

摘要： A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

公开(公告)号：US20230306101A1

公开(公告)日：2023-09-28

申请号：US18167070

申请日：2023-02-10

申请人： HONDA MOTOR CO.,LTD.

发明人： Yuki SAKAI ,  Yu YOSHII ,  Shoichi ITO ,  Ryosuke HORIE ,  Takato FUKUNO

IPC分类号： G06F21/44 ,  B60R16/023 ,  H04L67/12 ,  H04L7/00

CPC分类号： G06F21/44 ,  B60R16/0231 ,  H04L67/12 ,  H04L7/0016

摘要： A system includes a plurality of in-vehicle devices and having a function of determining abnormality of communication in the devices by authenticating a message including data, a first counter counted each time a power source is turned on, and a second counter incremented over time. The system includes an authentication unit for performing, when a message including control data to be exchanged between the devices is authenticated, authentication on a message sent and received between the devices and including at least the control data and the first counter by using at least the control data and the first counter, in which when it is confirmed whether synchronization is achieved between the devices, the authentication unit is for performing authentication on a message sent and received between the devices and not including the first counter but including the second counter by using the second counter without using the first counter.