Capacitance measurement circuit
    2.
    发明授权

    公开(公告)号:US12092672B2

    公开(公告)日:2024-09-17

    申请号:US17964847

    申请日:2022-10-12

    发明人: Yi-Chou Huang

    IPC分类号: G01R27/26 H03F3/45 H03M3/00

    摘要: A capacitance measure circuit includes a charge to voltage converter (CVC), and the CVC includes an excitation signal generation circuit that is arranged to generate and connect an excitation signal to a first terminal of a capacitance sensor, a differential amplifier, a first switch circuit, and at least one first variable capacitor. The inverting input terminal of the differential amplifier is arranged to receive a sensing capacitance value from a second terminal of the capacitance sensor. The first switch circuit is coupled between the inverting input terminal and the non-inverting output terminal of the differential amplifier, and is connected in parallel with the at least one first variable capacitor at the inverting input terminal and the non-inverting output terminal of the differential amplifier.

    READOUT CIRCUIT FOR HIGH-PRECISION VIBRATION SENSOR

    公开(公告)号:US20240186969A1

    公开(公告)日:2024-06-06

    申请号:US18319411

    申请日:2023-05-17

    摘要: A readout circuit for a high-precision vibration sensor comprises an on-chip self-test circuit, a low-noise charge amplifier, a correlated double sampling circuit, a PID feedback control circuit, a phase compensation circuit and Sigma-Delta. A self-test signal is amplified by the low-noise charge amplifier, low-frequency noise and offsets are filtered out by the correlated double sampling circuit, then a self-test path and a working path of a vibration sensor are separated in the time domain by the PID feedback control circuit, the phase compensation circuit performs zero compensation and pole compensation on the signal, and Sigma-Delta converts an analog signal into a high-precision digital signal.

    Loop delay compensation in a delta-sigma modulator

    公开(公告)号:US11929765B2

    公开(公告)日:2024-03-12

    申请号:US17380356

    申请日:2021-07-20

    发明人: Meghna Agrawal

    IPC分类号: H03M3/00 H03M1/12

    摘要: A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

    Circuit for measuring a resistance

    公开(公告)号:US11789054B2

    公开(公告)日:2023-10-17

    申请号:US16977313

    申请日:2019-03-12

    IPC分类号: G01R27/14 H03K17/687 H03M3/00

    摘要: A circuit for measuring an unknown resistance of a resistive element comprises a sensor circuit to generate a differential voltage dependent on the resistance of the resistive element and a reference circuit to generate a differential reference voltage and a sigma-delta converter comprising a first stage, wherein a first capacitor is selectively coupled to one of the output terminals of the sensor circuit and a second capacitor is coupled to one of the output terminals of the reference circuit. The circuit generates logarithmically compressed values.

    Circuitry and methods for fractional division of high-frequency clock signals

    公开(公告)号:US11784651B2

    公开(公告)日:2023-10-10

    申请号:US17512231

    申请日:2021-10-27

    申请人: NXP B.V.

    摘要: An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.

    Signal Processing Unit and Method for Time of Flight Measurement

    公开(公告)号:US20190107608A1

    公开(公告)日:2019-04-11

    申请号:US15727376

    申请日:2017-10-06

    发明人: Paul Ta

    IPC分类号: G01S7/486 H04B10/61

    摘要: A signal processing unit for time of flight measurement includes an oscillation module, a transmission module, a detection module, a multiplier, an analog-to-digital-converter and a processing module. The oscillation module provides m reference phases. The transmission module generates a set of light impulses based on a selection phase selected out of the m reference phases. The detection module receives a set of reflections of the set of light impulses and to generate a detector signal based on the set of reflections. The multiplier obtains a result of a multiplication of the detector signal by a comparison phase. The analog-to-digital-converter converts the result of the multiplier into a digital signal. The processing module determines the comparison phase or the selection phase and calculates an approximate phase difference between the set of generated light impulses and the set of received reflections based on the digital signal.