-
公开(公告)号：US11329662B2
公开(公告)日：2022-05-10
申请号：US16985104
申请日：2020-08-04
Applicant: Intel Corporation
Inventor： Yitzhak Elhanan Schifmann , Yoel Krupnik , Ariel Cohen
Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
-
公开(公告)号：US10742227B1
公开(公告)日：2020-08-11
申请号：US16285060
申请日：2019-02-25
Applicant: Intel Corporation
Inventor： Yitzhak Elhanan Schifmann , Yoel Krupnik , Ariel Cohen
Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
-
公开(公告)号：US09857814B2
公开(公告)日：2018-01-02
申请号：US14129273
申请日：2013-09-27
Applicant: Intel Corporation
Inventor： Ariel Cohen , Yoav Romach , Omer Cohen , Ro'ee Eitan
CPC classification number: G05F1/56 , G01K7/00 , G01K7/01 , G01K2215/00 , G05F1/468 , G05F1/567 , G06F1/26 , H02M3/07
Abstract: Apparatus of a supply generator using dynamic circuit reference is provided which includes: a charge pump to receive a first power supply and to generate a second power supply; a voltage regulator to operate using the second power supply, the voltage regulator having an input to receive a reference and to generate a third power supply; and a reference generator to operate using the first power supply, the reference generator to provide the reference according to an output of a voltage sensing block.
-
公开(公告)号：US10855305B2
公开(公告)日：2020-12-01
申请号：US16375572
申请日：2019-04-04
Applicant: Intel Corporation
Inventor： Roee Eitan , Ahmad B. Khairi , Yosi Sanhedrai , Ram Livne , Ilya Kraimer , Hen Sallem , Idan Lotan , Ariel Cohen , Dror Lazar
Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.
-
5.发明授权公开(公告)号：US10340938B1
公开(公告)日：2019-07-02
申请号：US15961460
申请日：2018-04-24
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
-
Patent Agency Ranking
公开(公告)号：US20210152404A1
公开(公告)日：2021-05-20
申请号：US17127853
申请日：2020-12-18
Applicant: Intel Corporation
Inventor： Itamar Levin , Tali Warshavsky Grafi , Marco Cusmai , Ajay Balankutty , FNU Shiva Kiran , Ariel Cohen
IPC: H04L25/03
Abstract: An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope.
-
7.发明授权公开(公告)号：US10756747B2
公开(公告)日：2020-08-25
申请号：US16459421
申请日：2019-07-01
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
-
公开(公告)号：US09973356B1
公开(公告)日：2018-05-15
申请号：US15475690
申请日：2017-03-31
Applicant: Intel Corporation
Inventor： Ram Livne , Ro'ee Eitan , Yoel Krupnik , Vladislav Tsirkin , Tomer Fael , Dror Lazar , Ariel Cohen , Alexander Pogrebinsky , Adee Ofir Ran
CPC classification number: H04L25/03057
Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.
-
公开(公告)号：US11705916B2
公开(公告)日：2023-07-18
申请号：US17717558
申请日：2022-04-11
Applicant: Intel Corporation
Inventor： Yitzhak Elhanan Schifmann , Yoel Krupnik , Ariel Cohen
CPC classification number: H03M1/121 , G11C27/02 , H03F3/213 , H03F3/68 , H03M1/1245 , H03M1/38 , H04B1/16 , H03F2200/129 , H03F2200/231 , H03F2200/267 , H03F2200/69
Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
-
10.发明申请公开(公告)号：US20190326922A1
公开(公告)日：2019-10-24
申请号：US16459421
申请日：2019-07-01
Applicant: Intel Corporation
Inventor： Roee Eitan , Ram Livne , Ahmad Khairi , Yoel Krupnik , Ariel Cohen
Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.012 seconds)
