公开(公告)号：US12014152B2

公开(公告)日：2024-06-18

申请号：US17334816

申请日：2021-05-31

申请人： Redpine Signals, Inc.

发明人： Martin Kraemer ,  Ryan Boesch ,  Wei Xiong

IPC分类号： G06F7/544 ,  H03K19/20 ,  H03M1/38 ,  H03M3/04

CPC分类号： G06F7/5443 ,  H03K19/20 ,  H03M1/38 ,  H03M3/04

摘要： A Unit Element (UE) has a digital X input and a digital W input, and comprises groups of NAND gates generating complementary outputs which are coupled to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The number of bits in the X input determines the number of NAND gates in a NAND-group and the number of bits in the W input determines the number of NAND groups. Each NAND-group receives one bit of the W input applied to all of the NAND gates of the NAND-group, and each unit element having the bits of X applied to each associated NAND gate input of each unit element. The NAND gate outputs are coupled through binary weighted charge transfer capacitors to a positive charge transfer line and negative charge transfer line.

公开(公告)号：US20220312045A1

公开(公告)日：2022-09-29

申请号：US17839060

申请日：2022-06-13

申请人： CABLE TELEVISION LABORATORIES, INC.

发明人： ZHENSHENG JIA ,  LUIS ALBERTO CAMPOS ,  MU XU ,  JING WANG

IPC分类号： H04N19/94 ,  H04N19/126 ,  H03M3/00 ,  H04J14/04 ,  H03M1/00 ,  H03M3/04 ,  H03M1/66 ,  H03M1/12 ,  H03M7/30

摘要： An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

公开(公告)号：US10763885B2

公开(公告)日：2020-09-01

申请号：US16675051

申请日：2019-11-05

申请人： STMicroelectronics S.r.l.

发明人： Marta Gómez Correa ,  Fabio Dell'Orto ,  Muhammad Umair Saeed

IPC分类号： H04B14/06 ,  H03M3/04 ,  G10L19/04 ,  G10L19/008 ,  H03M7/36 ,  G10L19/005

摘要： In an embodiment, a method includes: receiving an audio frame; decomposing the received audio frame into M sub-band pulse-code modulation (PCM) audio frames, where M is a positive integer number; predicting a PCM sample of one sub-band PCM audio frame of the M sub-band PCM audio frames; comparing the predicted PCM sample with a corresponding received PCM sample to generate a prediction error sample; comparing an instantaneous absolute value of the prediction error sample with a threshold; and replacing the corresponding received PCM sample with a value based on the predicted PCM sample when the instantaneous absolute value of the prediction error sample is greater than the threshold.

公开(公告)号：US10699725B2

公开(公告)日：2020-06-30

申请号：US15151109

申请日：2016-05-10

申请人： Immersion Services LLC

发明人： James D. Johnston ,  Stephen White

IPC分类号： G10L19/04 ,  H03M7/38 ,  H03M3/04

摘要： An encoder includes a low-pass filter to filter input audio signals. The low-pass filter has fixed filter coefficients. The encoder generates quantized signals based on a difference signal. The encoder includes an adaptive quantizer and a decoder to generate feedback signals. The decoder has an inverse quantizer and a predictor. The predictor has fixed control parameters which are based on a frequency response of the low-pass filter. The predictor may include a finite impulse response filter having fixed filter coefficients. The decoder may include an adaptive noise shaping filter coupled between the low-pass filter and the encoder. The adaptive noise shaping filter flattens signals within a frequency spectrum corresponding to a frequency spectrum of the low-pass filter.

公开(公告)号：US09520894B1

公开(公告)日：2016-12-13

申请号：US14836916

申请日：2015-08-26

申请人： The Boeing Company

发明人： Amir L. Liaghati

IPC分类号： H03M7/32 ,  H03M3/04 ,  H03M7/30

CPC分类号： H03M3/04

摘要： A signal encoding and compression system with dynamic downsampling may include an encoder module configured to decimate a first digital signal, thereby producing a second digital signal. Each signal may then be DPCM-encoded. Decision logic may then be used to determine which encoded signal to provide as an output, based on a characteristic of the original signal.

摘要翻译： 具有动态下采样的信号编码和压缩系统可以包括被配置为抽取第一数字信号的编码器模块，从而产生第二数字信号。 然后可以对每个信号进行DPCM编码。 然后，决定逻辑可以用于基于原始信号的特性来确定要提供作为输出的编码信号。

公开(公告)号：US20100321221A1

公开(公告)日：2010-12-23

申请号：US12870135

申请日：2010-08-27

申请人： Giri NK. Rangan ,  Roger Levinson ,  John M. Caruso

发明人： Giri NK. Rangan ,  Roger Levinson ,  John M. Caruso

IPC分类号： H03M3/04

CPC分类号： H03M3/428 ,  H03M3/452

摘要： A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer.

摘要翻译： Σ-Δ转换器系统和方法包括耦合到转换器的输出端的多位量化器电路。 单个位模数转换器电路包含在转换器的反馈路径中。 该转换器包括前馈路径，其可操作以将输入电压乘以具有作为增益控制输入信号的函数的值的前馈系数。 增益控制输入信号可以具有作为多位量化器的输出的函数的值。

公开(公告)号：US20090109076A1

公开(公告)日：2009-04-30

申请号：US11926148

申请日：2007-10-29

申请人： SAKET JALAN

发明人： SAKET JALAN

IPC分类号： H03M3/04

CPC分类号： H03M7/3022

摘要： A Multi-stage noise shaping Sigma Delta Modulator (MSDM) and method of processing data using the MSDM are disclosed. The MSDM is capable of operating at high radio frequencies and is characterized by low power consumption, reduced latency and noise and occupies less area in an integrated circuit.

摘要翻译： 公开了使用MSDM处理数据的多级噪声整形ΣΔ调制器（MSDM）和方法。 MSDM能够在高无线电频率下工作，其特征在于低功耗，降低延迟和噪声，并且在集成电路中占据较少的面积。

公开(公告)号：US20080297385A1

公开(公告)日：2008-12-04

申请号：US11661627

申请日：2004-09-02

申请人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

发明人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

IPC分类号： H03M3/04

CPC分类号： H03M3/394 ,  H03M3/406 ,  H03M3/424 ,  H03M3/452

摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.

摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。

公开(公告)号：US20080055133A1

公开(公告)日：2008-03-06

申请号：US11895630

申请日：2007-08-24

申请人： Shantanu Chakrabartty

发明人： Shantanu Chakrabartty

IPC分类号： H03M3/04

CPC分类号： H03M3/466

摘要： A method is provided for multi-channel analog-to-digital conversion. The method includes: receiving an input vector which represents a plurality of analog signals; transforming the input vector using a linear transformation matrix; converting the transformed input vector to a digital stream using an array of sigma-delta converter; and adapting the linear transform matrix to maximize de-correlation between the signals represented in the input vector.

摘要翻译： 提供了一种用于多通道模数转换的方法。 该方法包括：接收表示多个模拟信号的输入向量; 使用线性变换矩阵变换输入向量; 使用Σ-Δ转换器的阵列将变换的输入向量转换为数字流; 并适应线性变换矩阵以最大化在输入向量中表示的信号之间的去相关。

公开(公告)号：US20070290907A1

公开(公告)日：2007-12-20

申请号：US10590401

申请日：2005-02-04

申请人： Lukas Doerrer ,  Franz Kuttner

发明人： Lukas Doerrer ,  Franz Kuttner

IPC分类号： H03M3/04

CPC分类号： H03M3/424 ,  H03M1/182 ,  H03M3/392

摘要： The invention relates to a power-saving multibit delta-sigma converter (1) comprising: an input (2) for an analog input signal (ZA) and an output (3) for a digital output signal (ZD); a digital-to-analog converter (4) having a bit width N and serving to convert the digital output signal (ZD) to an analog feedback signal (Z3); a summing device (5) for solving the difference between the input signal (ZA) and the feedback signal (Z3); a filter (6) for filtering the difference signal (Z1); and a clocked quantizing device (7) for quantizing the filtered difference signal (Z2) into a digital output signal (ZD) with the bit width N. Said quantizing device (7) comprises a number of comparators (21, 22, 23) that compare the filtered signal (Z2) with a respective reference potential (U0, U6) associated with each comparator (21, 22, 23) and they each output a comparison result (V1, V2, V3) to a decoder (33), which generates the digital output signal (ZD) from the comparison results (V1, V2, V3), and the reference potentials (U0, . . . U6) are updated according to a previous comparison result.

摘要翻译： 本发明涉及一种节能多位Δ-Σ转换器（1），包括：用于模拟输入信号（ZA）的输入（2）和用于数字输出信号（ZD）的输出（3）; 具有位宽N并用于将数字输出信号（ZD）转换为模拟反馈信号（Z 3）的数模转换器（4）; 用于求解输入信号（ZA）和反馈信号（Z 3）之间的差的求和装置（5）; 滤波器（6），用于滤除差分信号（Z 1）; 以及用于将经滤波的差分信号（Z 2）量化为具有位宽度N的数字输出信号（ZD）的时钟量化装置（7）。所述量化装置（7）包括多个比较器（21,22,23） 其将经滤波的信号（Z 2）与与每个比较器（21,22,23）相关联的相应参考电位（U 0，U 6）进行比较，并且它们各自输出比较结果（V 1，V 2，V 3）到 根据比较结果（V 1，V 2，V 3）和参考电位（U 0，... U 6）生成数字输出信号（ZD）的解码器（33）根据前一个 比较结果。