公开(公告)号：US20160056837A1

公开(公告)日：2016-02-25

申请号：US14592736

申请日：2015-01-08

Applicant: INTERSIL AMERICAS LLC

Inventor： Anthony John Allen

IPC: H03M3/00 ,  H03K19/0175

CPC classification number: H03M3/394 ,  H02J7/008 ,  H02J7/022 ,  H02J7/345 ,  H03K19/017509 ,  H03M1/12 ,  H03M3/30 ,  H03M3/454 ,  H03M3/464 ,  H03M3/472 ,  Y02E60/12

Abstract: A system, circuit and method for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal are disclosed. For example, a circuit for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal is disclosed, which includes a comparator configured to receive a differential voltage signal including a high common mode voltage component and output a digital signal associated with the differential voltage signal, a level shifter configured to receive the digital signal and shift the level of the digital signal to a low level, an integrator configured to receive the digital low level signal and output a ramping voltage associated with the low level signal, and an analog-to-digital converter configured to receive the ramping voltage and output a digital bit-stream associated with the ramping voltage.

Abstract translation: 公开了一种用于将包括高共模电压分量的差分电压信号转换为接地参考信号的系统，电路和方法。 例如，公开了一种用于将包括高共模电压分量的差分电压信号转换为接地参考信号的电路，其包括比较器，其被配置为接收包括高共模电压分量的差分电压信号，并输出相关的数字信号 利用差分电压信号，电平移位器被配置为接收数字信号并将数字信号的电平移位到低电平，积分器被配置为接收数字低电平信号并输出​​与低电平信号相关联的斜坡电压， 以及被配置为接收斜坡电压并输出与斜坡电压相关联的数字比特流的模数转换器。

公开(公告)号：US08749417B2

公开(公告)日：2014-06-10

申请号：US13344143

申请日：2012-01-05

Applicant: Abdulkerim L. Coban ,  Clayton H. Daigle ,  Alessandro Piovaccari

Inventor： Abdulkerim L. Coban ,  Clayton H. Daigle ,  Alessandro Piovaccari

IPC: H03M3/00 ,  H03M1/12 ,  H03M7/20

CPC classification number: H03M3/394 ,  H03M3/396 ,  H03M3/398 ,  H03M3/40 ,  H03M3/448 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454 ,  H04N21/6112 ,  H04N21/6118 ,  H04N21/6143

Abstract: A method of configuring an analog-to-digital converter (ADC) includes configuring the ADC to operate in one of a low-pass filter mode and a band-pass filter mode according to a value of a control signal. In at least one embodiment, the method further includes configuring an integrator gain of the ADC and a feed-forward gain of the ADC based on selection of one of a low-intermediate frequency (LIF) mode and a zero-intermediate frequency (ZIF) mode.

Abstract translation: 配置模数转换器（ADC）的方法包括根据控制信号的值将ADC配置为以低通滤波器模式和带通滤波器模式之一工作。 在至少一个实施例中，该方法还包括基于选择低中频（LIF）模式和零中频（ZIF）之一来配置ADC的积分器增益和ADC的前馈增益， 模式。

公开(公告)号：US07605731B2

公开(公告)日：2009-10-20

申请号：US11577500

申请日：2005-10-11

Applicant: Robert Henrikus Margaretha Van Veldhoven

Inventor： Robert Henrikus Margaretha Van Veldhoven

IPC: H03M1/62 ,  H03M1/84

CPC classification number: H03M3/394 ,  H03M3/424 ,  H03M3/452 ,  H03M3/462

Abstract: A signal processing circuit has an analog to digital converter (31) for providing a digital signal to a processor (15) from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) controlled by a gain control signal based on detected signal strength. The analog to digital converter has a loop comprising a loop filter for processing the input signal. A signal strength detection circuit (32) is provided for generating the gain control signal, which signal strength detection circuit has loop signal detector for detecting the signal strength from the loop. Hence a received signal strength indicator RSSI is directly coupled to the analog to digital converter (31), avoiding the delay of signal strength detection in the digital processor.

Abstract translation: 信号处理电路具有模数转换器（31），用于从容易受信号功率变化影响的模拟输入信号（15）提供数字信号给处理器（15）。 从无线电前端（12）。 该装置具有基于检测到的信号强度由增益控制信号控制的可变增益放大器（13）。 模数转换器具有包括用于处理输入信号的环路滤波器的回路。 提供信号强度检测电路（32），用于产生增益控制信号，该信号强度检测电路具有环路信号检测器，用于检测来自环路的信号强度。 因此，接收的信号强度指示器RSSI直接耦合到模数转换器（31），避免了数字处理器中信号强度检测的延迟。

公开(公告)号：US09553124B2

公开(公告)日：2017-01-24

申请号：US14939852

申请日：2015-11-12

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives

Inventor： Arnaud Verdant

IPC: H03M3/00 ,  H01L27/146 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H01L27/14643 ,  H01L27/14612 ,  H01L27/14636 ,  H03M3/394 ,  H03M3/458 ,  H04N5/37455 ,  H04N5/378

Abstract: A CMOS image sensor including a plurality of pixels, each including: a photodiode; a sigma-delta modulator of order p, p being an integer greater than or equal to 1, capable of delivering a binary digital signal representative of the illumination level of the photodiode; and a configurable connection circuit enabling to couple the sigma-delta modulator of the pixel to a sigma-delta modulator of another pixel, so that the modulators of the two pixels form with each other a sigma-delta modulator of order greater than p.

Abstract translation: 包括多个像素的CMOS图像传感器，每个像素包括：光电二极管; 阶数p的Σ-Δ调制器，p是大于或等于1的整数，能够传送表示光电二极管的照明级的二进制数字信号; 以及能够将像素的Σ-Δ调制器耦合到另一个像素的Σ-Δ调制器的可配置连接电路，使得两个像素的调制器彼此形成大于p的阶数的Σ-Δ调制器。

公开(公告)号：US20140368368A1

公开(公告)日：2014-12-18

申请号：US14368040

申请日：2012-12-29

Applicant: ST-Ericsson SA

Inventor： Kimmo Koli

IPC: H03M3/00 ,  H03M1/06

CPC classification number: H03M3/462 ,  H03M1/06 ,  H03M3/394 ,  H03M3/414 ,  H03M3/436 ,  H03M3/496

Abstract: Continuous-time MASH sigma-delta ADC with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

Abstract translation: 具有1.5位的第一调制器和1位的第二调制器的连续时间MASHΣ-ΔADC也接收来自另一个调制器的反馈。 在第二调制器处采样速率较高，并且在将其输出与第一调制器的输出相加之前进行抽取。

公开(公告)号：US20110148679A1

公开(公告)日：2011-06-23

申请号：US12981722

申请日：2010-12-30

Applicant: Udo Karthaus ,  Stephan Ahles

Inventor： Udo Karthaus ,  Stephan Ahles

IPC: H03M3/02 ,  H05K13/00

CPC classification number: H03M3/396 ,  H03M3/394 ,  H03M3/408 ,  H03M3/43 ,  H03M3/454 ,  Y10T29/49002

Abstract: A delta-sigma modulator is disclosed which has a filter comprising a filter input, two LC resonators (LC1-1, LC1-2), and two switches (CBT/CGT). An input of each one of the two switches is connected to the filter input and a corresponding output of each one of the two switches is connected to a corresponding one of said LC resonators. Each one of the two switches is individually controllable for selectively connecting the corresponding one of the LC resonators with the filter input. The invention also relates to a method for changing the mode of operation of a delta-sigma modulator.

Abstract translation: 公开了一种Δ-Σ调制器，其具有包括滤波器输入，两个LC谐振器（LC1-1，LC1-2）和两个开关（CBT / CGT）的滤波器。 两个开关中的每一个的输入连接到滤波器输入，并且两个开关中的每一个的相应输出连接到所述LC谐振器中的相应一个。 两个开关中的每一个都是可单独控制的，用于选择性地将LC谐振器中的一个与滤波器输入连接。 本发明还涉及一种用于改变Δ-Σ调制器的操作模式的方法。

公开(公告)号：US20080297388A1

公开(公告)日：2008-12-04

申请号：US12060128

申请日：2008-03-31

Applicant: Eashwar Thiagarajan ,  Mohandas Palatholmana Sivadasan ,  Gajender Rohilla ,  Harold Kutz ,  Monte Mar

Inventor： Eashwar Thiagarajan ,  Mohandas Palatholmana Sivadasan ,  Gajender Rohilla ,  Harold Kutz ,  Monte Mar

IPC: H03M3/02

CPC classification number: H03M3/394 ,  H03M3/438

Abstract: A system includes an analog-to-digital modulator to convert at least one analog input signal into at least one digital output signal. The system also includes a processing device to set an operational order and a quantization level of the analog-to-digital modulator. The analog-to-digital modulator converts the analog input signal into the digital output signal according to the operational order and the quantization level.

Abstract translation: 一种系统包括将至少一个模拟输入信号转换成至少一个数字输出信号的模拟 - 数字调制器。 该系统还包括用于设置模数转换器的操作顺序和量化电平的处理装置。 模拟数字调制器根据操作顺序和量化级将模拟输入信号转换为数字输出信号。

公开(公告)号：US20080218392A1

公开(公告)日：2008-09-11

申请号：US11577499

申请日：2005-10-11

Applicant: Robert Henrikus Margaretha Van Veldhoven ,  Lucien Johannes Breems

Inventor： Robert Henrikus Margaretha Van Veldhoven ,  Lucien Johannes Breems

IPC: H04M3/04 ,  H03M3/00

CPC classification number: H03M3/394 ,  H03M3/424 ,  H03M3/452 ,  H03M3/462

Abstract: A signal receiver processing circuit is for isolating a desired signal from analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) and an analog to digital converter (14) for providing a digital signal to a digital signal processor (15), the digital signal processor including a digital filter. The device has a control unit (16) for adjusting a filtering accuracy of the analog to digital converter (14) and/or the digital signal processor unit (15) in dependence of a signal quality of the input signal.

Abstract translation: 信号接收机处理电路用于将期望的信号与容易受信号功率变化影响的模拟输入信号进行隔离。 从无线电前端（12）。 该装置具有可变增益放大器（13）和用于向数字信号处理器（15）提供数字信号的模数转换器（14），数字信号处理器包括数字滤波器。 该装置具有控制单元（16），用于根据输入信号的信号质量来调节模数转换器（14）和/或数字信号处理器单元（15）的滤波精度。

公开(公告)号：US06765517B1

公开(公告)日：2004-07-20

申请号：US09616634

申请日：2000-07-26

Applicant: Danish Ali

Inventor： Danish Ali

IPC: H03M110

CPC classification number: H03M3/394 ,  H03M3/454

Abstract: A Sigma-Delta modulator(10) comprises a signal put(34) coupled to a forward filter comprising a series connection of a plurality of N summing stages(28, 30, 32), where N is an integer of at least 2, alternating with a corresponding plurality of integrating stages(40, 42, 44) and an analogue to digital converter(ADC)(18) having an input coupled to an output of the Nth integrating stage(44) and an output. A feedback filter comprises a feedback coupling from the output of the ADC(18) to a digital to analogue converter(DAC)(26) which is coupled to an input of each of the summing stages by way of respective weights(46, 48, 50). Control means(66) including switching means (58, 64) are provided for changing the order of the modulator. To reduce the order and increase the bandwidth, the control means by-passes the first(40) of the integrating stages and uses the second(42) of the integrating stages as a first of the integrating stages and vice versa to increase the order and decrease the bandwidth.

Abstract translation: Σ-Δ调制器（10）包括耦合到正向滤波器的信号放大器（34），其包括多个N个加法级（28,30,32）的串联连接，其中N是至少为2的整数，交替地 具有对应的多个积分级（40,42,44）和模数转换器（ADC）（18），其具有耦合到第N个积分级（44）的输出的输入和输出。 反馈滤波器包括从ADC（18）的输出到数模转换器（DAC）（26）的反馈耦合，其通过相应的权重（46,48,48）耦合到每个求和级的输入， 50）。 提供包括切换装置（58,64）的控制装置（66），用于改变调制器的次序。 为了减小顺序并增加带宽，控制装置绕过积分级的第一（40），并且使用积分级的第二（42）作为积分级的第一级，反之亦然，以增加顺序和 降低带宽。

公开(公告)号：US20160141327A1

公开(公告)日：2016-05-19

申请号：US14939852

申请日：2015-11-12

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives

Inventor： Arnaud Verdant

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14612 ,  H01L27/14636 ,  H03M3/394 ,  H03M3/458 ,  H04N5/37455 ,  H04N5/378

Abstract: A CMOS image sensor including a plurality of pixels, each including: a photodiode; a sigma-delta modulator of order p, p being an integer greater than or equal to 1, capable of delivering a binary digital signal representative of the illumination level of the photodiode; and a configurable connection circuit enabling to couple the sigma-delta modulator of the pixel to a sigma-delta modulator of another pixel, so that the modulators of the two pixels form with each other a sigma-delta modulator of order greater than p.

Abstract translation: 包括多个像素的CMOS图像传感器，每个像素包括：光电二极管; 阶数p的Σ-Δ调制器，p是大于或等于1的整数，能够传送表示光电二极管的照明级的二进制数字信号; 以及能够将像素的Σ-Δ调制器耦合到另一个像素的Σ-Δ调制器的可配置连接电路，使得两个像素的调制器彼此形成大于p的阶数的Σ-Δ调制器。