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    Voltage controlled oscillator delay cell and method
    1.
    发明授权
    Voltage controlled oscillator delay cell and method 有权
    压控振荡器延时单元及方法

    公开(公告)号：US07400183B1

    公开(公告)日：2008-07-15

    申请号：US11415588

    申请日：2006-05-01

    申请人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

    发明人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

    IPC分类号： H03H11/26

    CPC分类号： H03H11/265 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L7/0995

    摘要： A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

    摘要翻译： 公开了一种延迟单元电路（200）。 延迟单元电路可以包括差分级（202）和交叉耦合级（204）。 交叉耦合级可以包括用于减小增益的功能的电阻器（210-0和210-1）。 差分级（202）和交叉耦合级（204）可分别包括可变电流源（208和212）。 随着操作频率的增加，可变电流源（208）向差分级（202）提供更大的电流，并且可变电流源（212）向交叉耦合级（204）提供较小的电流。 延迟单元电路（200）可以用在压控振荡器（VCO）中。 通过包括诸如电阻器（210-0和210-1）的增益衰减器件，可以增加VCO的频率调谐范围。

    Programmable buffer circuit
    4.
    发明授权
    Programmable buffer circuit 有权
    可编程缓冲电路

    公开(公告)号：US08941410B1

    公开(公告)日：2015-01-27

    申请号：US13303105

    申请日：2011-11-22

    申请人： Gajender Rohilla ,  Eashwar Thiagarajan ,  Harold Kutz ,  Monte Mar ,  Mohandas Palatholmana Sivadasan

    发明人： Gajender Rohilla ,  Eashwar Thiagarajan ,  Harold Kutz ,  Monte Mar ,  Mohandas Palatholmana Sivadasan

    IPC分类号： H03K19/0175 ,  H03K17/00

    CPC分类号： H03K19/018585 ,  H03F3/387 ,  H03F3/45183 ,  H03M1/124 ,  H03M1/129

    摘要： Buffer circuit embodiments are described. A buffer circuit includes an input configured to receive an input signal and a buffer configured to generate an output signal based on the input signal. In one embodiment, the buffer circuit includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration. In another embodiment, the buffer circuit further includes a programmable output filter coupled with the buffer, wherein the programmable output filter is programmable with a selected configuration form a plurality of configurations, and wherein the programmable output filter filters a frequency band of the output signal based on the selected configuration.

    摘要翻译： 描述缓冲电路实施例。 缓冲电路包括被配置为接收输入信号的输入和被配置为基于输入信号产生输出信号的缓冲器。 在一个实施例中，缓冲电路包括与缓冲器耦合的可编程斩波模块，其中可编程斩波模块可根据多种配置以选定的配置进行编程，并且其中可编程斩波基于所选择的配置来调制输入信号。 在另一个实施例中，缓冲电路还包括与缓冲器耦合的可编程输出滤波器，其中可编程输出滤波器可以由多个配置形式的选定配置编程，并且其中可编程输出滤波器基于输出信号的频带 对所选配置。

    Voltage controlled oscillator delay cell and method
    5.
    发明授权
    Voltage controlled oscillator delay cell and method 有权
    压控振荡器延时单元及方法

    公开(公告)号：US08120408B1

    公开(公告)日：2012-02-21

    申请号：US12218404

    申请日：2008-07-14

    申请人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

    发明人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

    IPC分类号： H03H11/26

    CPC分类号： H03H11/265 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L7/0995

    摘要： A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

    摘要翻译： 公开了一种延迟单元电路（200）。 延迟单元电路可以包括差分级（202）和交叉耦合级（204）。 交叉耦合级可以包括用于减小增益的功能的电阻（210-0和210-1）。 差分级（202）和交叉耦合级（204）可分别包括可变电流源（208和212）。 随着操作频率的增加，可变电流源（208）向差分级（202）提供更大的电流，并且可变电流源（212）向交叉耦合级（204）提供较小的电流。 延迟单元电路（200）可以用在压控振荡器（VCO）中。 通过包括诸如电阻（210-0和210-1）的增益衰减器件，可以增加VCO的频率调谐范围。

    Programmable buffer circuit
    6.
    发明授权
    Programmable buffer circuit 有权
    可编程缓冲电路

    公开(公告)号：US08063665B1

    公开(公告)日：2011-11-22

    申请号：US12496612

    申请日：2009-07-01

    申请人： Gajender Rohilla ,  Eashwar Thiagarajan ,  Harold Kutz ,  Monte Mar ,  Mohandas Palatholmana Sivadasan

    发明人： Gajender Rohilla ,  Eashwar Thiagarajan ,  Harold Kutz ,  Monte Mar ,  Mohandas Palatholmana Sivadasan

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018585 ,  H03F3/387 ,  H03F3/45183 ,  H03M1/124 ,  H03M1/129

    摘要： A buffer circuit includes an input configured to receive an input signal; and a buffer configured to generate an output signal based on the input signal. In an embodiment, the output signal has a linear relationship with the input signal when the input signal is within the input voltage range; and the buffer circuit further includes a level-shifting circuit coupled with the input, wherein the level shifting circuit determines an input voltage range, and wherein one of an upper limit and a lower limit of the input voltage range is within 50 millivolts from a supply rail voltage. In another embodiment, the buffer circuit further includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration. In yet another embodiment, the buffer circuit further includes a programmable output filter coupled with the buffer, wherein the programmable output filter is programmable with a selected configuration from a plurality of configurations, and wherein the programmable output filter filters a frequency band of the output signal based on the selected configuration.

    摘要翻译： 缓冲电路包括被配置为接收输入信号的输入; 以及配置为基于所述输入信号生成输出信号的缓冲器。 在一个实施例中，当输入信号在输入电压范围内时，输出信号与输入信号具有线性关系; 并且所述缓冲电路还包括与所述输入端耦合的电平移动电路，其中所述电平移位电路确定输入电压范围，并且其中所述输入电压范围的上限和下限之一在电源的50毫伏之内 轨电压。 在另一个实施例中，缓冲电路还包括与缓冲器耦合的可编程斩波模块，其中可编程斩波模块可根据多种配置以选定的配置进行编程，并且其中可编程斩波基于所选择的配置来调制输入信号。 在另一个实施例中，缓冲电路还包括与缓冲器耦合的可编程输出滤波器，其中可编程输出滤波器可根据多种配置以选定的配置进行编程，并且其中可编程输出滤波器对输出信号的频带进行滤波 基于所选配置。