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    Modulator, phase locked loop using the same, and method applied thereto
    3.
    发明授权
    Modulator, phase locked loop using the same, and method applied thereto 有权
    调制器，使用其的锁相环，以及应用于其的方法

    公开(公告)号：US09584143B2

    公开(公告)日：2017-02-28

    申请号：US14943129

    申请日：2015-11-17

    申请人： MEDIATEK Inc.

    发明人： Yi-Chieh Huang ,  Ping-Ying Wang

    IPC分类号： H04L7/033 ,  H03L7/197 ,  H03C3/00

    CPC分类号： H03L7/1976 ,  H03C3/00 ,  H03C3/0933

    摘要： A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.

    摘要翻译： 提供了一种用于响应频率控制字产生控制码的调制器。 调制器包括加法器，累加器，下一个状态产生单元和代码生成单元。 加法器通过计算频率控制字和控制码之间的差异来产生频率误差信号。 累加器通过累加频率误差信号产生相位误差信号。 相位误差信号包括整数部分和小数部分。 相位误差信号的整数部分是当前状态信号。 下一个状态产生单元根据由相位误差信号的分数部分确定的特征概率分布产生下一个状态信号。 代码生成单元响应于当前状态信号和下一状态信号产生控制代码。

    Phase locked loop having fractional VCO modulation
    4.
    发明授权
    Phase locked loop having fractional VCO modulation 有权
    具有分数VCO调制的锁相环

    公开(公告)号：US09484936B2

    公开(公告)日：2016-11-01

    申请号：US14631305

    申请日：2015-02-25

    申请人： FREESCALE SEMICONDUCTOR, INC.

    发明人： Khurram Waheed ,  Kevin B. Traylor

    IPC分类号： H03C1/00 ,  H03C1/12 ,  H03L7/099 ,  H03L7/081 ,  H03B5/12 ,  H03M7/16 ,  H03M3/00 ,  H03C3/09 ,  H03C3/00 ,  H03L7/197

    CPC分类号： H03L7/099 ,  H03B5/124 ,  H03B5/1265 ,  H03C3/00 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03L7/081 ,  H03L7/197 ,  H03M3/422 ,  H03M7/165

    摘要： An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.

    摘要翻译： 集成电路包括双端口调制器和压控振荡器（VCO）。 双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的分数部分的第一输出端，​​用于提供高端口调制信号的整数部分的第二输出端和用于 提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收调谐信号的第三输入端 在低端口调制信号上，以及第一输出端用于输出RF信号。 双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号。

    INJECTION LOCKED RING OSCILLATOR BASED DIGITAL-TO-TIME CONVERTER AND METHOD FOR PROVIDING A FILTERED INTERPOLATED PHASE SIGNAL
    5.
    发明申请
    INJECTION LOCKED RING OSCILLATOR BASED DIGITAL-TO-TIME CONVERTER AND METHOD FOR PROVIDING A FILTERED INTERPOLATED PHASE SIGNAL 有权
    注射锁定振荡器基于数字时间转换器和提供过滤的内插相位信号的方法

    公开(公告)号：US20160173119A1

    公开(公告)日：2016-06-16

    申请号：US14570299

    申请日：2014-12-15

    申请人： Davide Ponton ,  Antonio Passamani ,  Andrea Bevilacqua

    发明人： Davide Ponton ,  Antonio Passamani ,  Andrea Bevilacqua

    IPC分类号： H03M1/66 ,  H04L27/233

    CPC分类号： H03M1/662 ,  G04F10/005 ,  H03C3/00 ,  H03K3/0315 ,  H03K5/131 ,  H03L7/0998 ,  H03M1/82 ,  H04L27/2331

    摘要： Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal.

    摘要翻译： 提供了数字到时间转换器（DTC）的装置和方法。 在示例中，DTC可以包括相位内插器和环形振荡器。 相位插值器可被配置为接收两个或多个不同相位信号的数字表示，并且内插两个或多个不同相位信号的数字表示以提供内插的输出相位信号。 环形振荡器可以被配置为接收内插相位信号，以锁定内插输出相位信号的频率和相位，并提供滤波相位信号。

    MICROPROCESSOR CONTROLLED CLASS E DRIVER
    8.
    发明申请
    MICROPROCESSOR CONTROLLED CLASS E DRIVER 有权
    微处理器控制类驱动程序

    公开(公告)号：US20150123608A1

    公开(公告)日：2015-05-07

    申请号：US14593781

    申请日：2015-01-09

    申请人： ALFRED E. MANN FOUNDATION FOR SCIENTIFIC RESEARCH

    发明人： Brian R. Dearden ,  James H. Wolfe ,  Manish Khemani

    IPC分类号： H02J7/02 ,  H02J7/00 ,  H04B5/00

    CPC分类号： H02J50/10 ,  A61N1/36125 ,  A61N1/37223 ,  A61N1/3727 ,  A61N1/3787 ,  H02J7/0052 ,  H02J7/007 ,  H02J7/025 ,  H02J50/80 ,  H02J2007/0096 ,  H03C3/00 ,  H04B5/0037

    摘要： A charger including a class E power driver, a frequency-shift keying (“FSK”) module, and a processor. The processor can receive data relating to the operation of the class E power driver and can control the class E power driver based on the received data relating to the operation of the class E power driver. The processor can additionally control the FSK module to modulate the natural frequency of the class E power transformer to thereby allow the simultaneous recharging of an implantable device and the transmission of data to the implantable device. The processor can additionally compensate for propagation delays by adjusting switching times.

    摘要翻译： 包括E类电源驱动器，频移键控（“FSK”）模块和处理器的充电器。 处理器可以接收与E类功率驱动器的操作有关的数据，并且可以基于与E类功率驱动器的操作相关的接收数据来控制E级功率驱动器。 处理器可以另外控制FSK模块来调制E类电力变压器的固有频率，从而允许可植入装置的同时充电以及将数据传输到可植入装置。 处理器可以通过调整切换时间来另外补偿传播延迟。