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    Phase locked loop having fractional VCO modulation
    4.
    发明授权
    Phase locked loop having fractional VCO modulation 有权
    具有分数VCO调制的锁相环

    公开(公告)号：US09484936B2

    公开(公告)日：2016-11-01

    申请号：US14631305

    申请日：2015-02-25

    申请人： FREESCALE SEMICONDUCTOR, INC.

    发明人： Khurram Waheed ,  Kevin B. Traylor

    IPC分类号： H03C1/00 ,  H03C1/12 ,  H03L7/099 ,  H03L7/081 ,  H03B5/12 ,  H03M7/16 ,  H03M3/00 ,  H03C3/09 ,  H03C3/00 ,  H03L7/197

    CPC分类号： H03L7/099 ,  H03B5/124 ,  H03B5/1265 ,  H03C3/00 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03L7/081 ,  H03L7/197 ,  H03M3/422 ,  H03M7/165

    摘要： An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.

    摘要翻译： 集成电路包括双端口调制器和压控振荡器（VCO）。 双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的分数部分的第一输出端，​​用于提供高端口调制信号的整数部分的第二输出端和用于 提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收调谐信号的第三输入端 在低端口调制信号上，以及第一输出端用于输出RF信号。 双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号。

    High-speed digital signal processing systems
    5.
    发明授权
    High-speed digital signal processing systems 有权
    高速数字信号处理系统

    公开(公告)号：US09337874B1

    公开(公告)日：2016-05-10

    申请号：US14575939

    申请日：2014-12-18

    申请人： Intel IP Corporation

    发明人： Chuanzhao Yu ,  Mark Kirschenmann

    IPC分类号： H03C1/00 ,  H04B1/04 ,  H04L27/20 ,  H03M7/16 ,  H03M1/66

    CPC分类号： H03M7/165 ,  H03M1/0863 ,  H03M1/687 ,  H03M1/804 ,  H04L27/00 ,  H04L27/20

    摘要： Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment, input binary bits are divided into two sets of bits, where one set is provided to a binary to thermometer coder to generate an output mixed with a clock signal to operatively provide a reverse order inverted bit pattern. The other set of binary bits is subject to exclusive-or processing such that processing of the two sets operatively provides a mixed hybrid code to be fed from high speed digital signal processor. Additional apparatus, systems, and methods are disclosed.

    摘要翻译： 提供高速数字信号处理器的装置和方法可以在基本上所有的数字发射机设计中实现。 在一个实施例中，输入二进制位被分成两组位，其中一组被提供给二进制到温度计编码器，以产生与时钟信号混合的输出，以可操作地提供反向反转位模式。 另一组二进制位被进行独占或处理，使得两组的处理可操作地提供要从高速数字信号处理器馈送的混合混合码。 公开了附加装置，系统和方法。

    Reference Voltage Generator for Temperature Sensor with Trimming Capability at Two Temperatures
    7.
    发明申请
    Reference Voltage Generator for Temperature Sensor with Trimming Capability at Two Temperatures 有权
    温度传感器参考电压发生器，具有两种温度下的微调功能

    公开(公告)号：US20150226614A1

    公开(公告)日：2015-08-13

    申请号：US14175226

    申请日：2014-02-07

    申请人： SanDisk Technologies Inc.

    发明人： Masahide Matsumoto ,  Ryuji Yamashita

    IPC分类号： G01K7/00 ,  H03M1/38 ,  G01K13/00

    CPC分类号： G01K15/005 ,  G01K7/00 ,  G01K7/01 ,  G01K13/00 ,  G01K2215/00 ,  G01K2219/00 ,  G05F3/245 ,  G11C7/04 ,  G11C16/06 ,  H03M1/12 ,  H03M1/38 ,  H03M7/165

    摘要： A temperature sensor circuit has a reference voltage generator that is trimmable at two temperatures for increased accuracy. The reference voltage generation section generates a reference voltage, the level of which is trimmable. A voltage divider section is connected to receive the reference voltage from the reference voltage generation section and generate a plurality of comparison voltage levels determined by the reference voltage and a trimmable resistance. An analog-to-digital converter can then be connected to a temperature dependent voltage section to receive the temperature dependent output voltage, such as a proportional to absolute temperature type (PTAT) behavior, and connected to the voltage divider section to receive the comparison voltage levels. The analog to digital converter generates an output indicative of the temperature based upon a comparison of the temperature dependent output voltage to the comparison voltage levels.

    摘要翻译： 温度传感器电路具有可在两个温度下调节的参考电压发生器，以提高精度。 参考电压产生部分产生可调整电平的参考电压。 连接分压器部分以从参考电压产生部分接收参考电压，并产生由参考电压和可调整电阻确定的多个比较电压电平。 然后可以将模数转换器连接到与温度相关的电压部分，以接收与温度相关的输出电压，例如与绝对温度类型（PTAT）的比例，并连接到分压器部分以接收比较电压 水平。 基于与温度相关的输出电压与比较电压电平的比较，模数转换器产生指示温度的输出。

    Analog to digital converter
    8.
    发明授权
    Analog to digital converter 有权
    模数转换器

    公开(公告)号：US09106248B1

    公开(公告)日：2015-08-11

    申请号：US14607282

    申请日：2015-01-28

    申请人： Huawei Technologies Co., Ltd.

    发明人： Mingjun Fan ,  Liming Fang ,  Yuan Liu

    IPC分类号： H03M1/34 ,  H03M1/12 ,  H03M7/16 ,  H03M1/00 ,  H03M1/36

    CPC分类号： H03M1/12 ,  H03M1/00 ,  H03M1/0602 ,  H03M1/365 ,  H03M7/165

    摘要： The present invention relates to an analog to digital converter. The analog to digital converter includes comparing modules at multi levels, where a comparing module at each level includes a comparator and a metastable state determining unit. The comparator is configured to, when a previous-level comparing module is not in a metastable state, receive a first clock, a first input signal, and a second input signal, and compare the first input signal with the second input signal. The metastable state determining unit is configured to, when the previous-level comparing module is not in a metastable state, receive the first clock, generate a reference clock according to the first clock, and if a second clock that is output by the comparator is later than the reference clock, determine that the current-level comparing module is in a metastable state.

    摘要翻译： 本发明涉及一种模数转换器。 模数转换器包括在多级别比较模块，其中每个级别的比较模块包括比较器和亚稳态确定单元。 比较器被配置为当前一级比较模块不处于亚稳状态时，接收第一时钟，第一输入信号和第二输入信号，并将第一输入信号与第二输入信号进行比较。 亚稳态确定单元被配置为当前级电平比较模块不处于亚稳态时，接收第一时钟，根据第一时钟生成参考时钟，并且如果由比较器输出的第二时钟是 晚于参考时钟，确定当前级别的比较模块处于亚稳状态。

    Successive approximation analog-to-digital converter with linearity error correction
    9.
    发明授权
    Successive approximation analog-to-digital converter with linearity error correction 有权
    具有线性误差校正的逐次逼近模数转换器

    公开(公告)号：US09071265B1

    公开(公告)日：2015-06-30

    申请号：US14457124

    申请日：2014-08-12

    申请人： Sanjoy K. Dey ,  Vikram Varma

    发明人： Sanjoy K. Dey ,  Vikram Varma

    IPC分类号： H03M1/10 ,  H03M1/14 ,  H03M1/12 ,  H03M1/80 ,  H03M1/06 ,  H03M1/00 ,  H03M7/16

    CPC分类号： H03M1/0695 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/12 ,  H03M1/468 ,  H03M1/804 ,  H03M7/165

    摘要： A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.

    摘要翻译： SAR ADC包括电容，比较器和SAR逻辑电路。 电容器包括第一组电容器和误差检测电容器。 第一组电容器产生第一组电压信号，该电压信号在第一组比较周期期间由比较器与共模电压信号（VCM）进行比较。 比较器产生第一组控制信号，由SAR逻辑电路用来连续近似第一组电压信号并产生第一组位。 误差检测电容器生成与比较器的共模电压信号VCM进行比较以产生检错控制信号的检错信号。 SAR逻辑电路基于错误检测控制信号的逻辑状态来补偿第一组位中的错误。

    ANALOG-DIGITAL CONVERTER
    10.
    发明申请
    ANALOG-DIGITAL CONVERTER 有权
    模拟数字转换器

    公开(公告)号：US20150180494A1

    公开(公告)日：2015-06-25

    申请号：US14405760

    申请日：2013-06-05

    申请人： KAGOSHIMA UNIVERSITY

    发明人： Kenichi Ohhata

    IPC分类号： H03M1/00 ,  H03M1/08 ,  H03M1/36

    CPC分类号： H03M1/002 ,  G02F7/00 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/0612 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/145 ,  H03M1/361 ,  H03M1/365 ,  H03M7/165

    摘要： A parallel-type AD converter includes: a plurality of comparators that receive comparison reference potentials different from one another and compare the comparison reference potentials and received analog input signals; an encoder that encodes outputs of the plurality of comparators to output digital signals; and a resistor ladder circuit that resistance-divides a reference voltage to generate the comparison reference potentials and supplies the comparison reference potentials to the comparators through output nodes each positioned between resistors, and is designed to supply a correction current corresponding to noise currents that the comparators generate to the output nodes of the comparison reference potentials in the resistor ladder circuit, and thereby the noise currents that the comparators generate are offset by the correction current, a bias current in the resistor ladder circuit can be decreased, and accuracy deterioration in AD conversion can be suppressed.

    摘要翻译： 并行型AD转换器包括：多个比较器，其接收彼此不同的比较参考电位，并比较比较参考电位和接收的模拟输入信号; 编码器，其对所述多个比较器的输出进行编码以输出数字信号; 以及电阻分压基准电压以产生比较参考电位的电阻梯形电路，并且通过每个位于电阻器之间的输出节点将比较参考电位提供给比较器，并且被设计为提供对应于噪声电流的校正电流，比较器 生成电阻梯形电路中比较参考电位的输出节点，从而比较器产生的噪声电流被校正电流偏移，电阻梯形电路中的偏置电流可能会降低，AD转换精度下降 可以抑制。